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1. Datasheet
2. Getting Started with the Arria V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Interrupts
7. Error Handling
8. IP Core Architecture
9. Transaction Layer Protocol (TLP) Details
10. Throughput Optimization
11. Design Implementation
12. Additional Features
13. Hard IP Reconfiguration
14. Transceiver PHY IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Document Revision History
1.1. Arria V Avalon-ST Interface for PCIe Datasheet
1.2. Features
1.3. Release Information
1.4. Device Family Support
1.5. Configurations
1.6. Example Designs
1.7. Debug Features
1.8. IP Core Verification
1.9. Performance and Resource Utilization
1.10. Recommended Speed Grades
1.11. Creating a Design for PCI Express
2.1.1. Generating the Testbench
2.1.2. Simulating the Example Design
Disabling Scrambling for Gen1 and Gen2 to Interpret TLPs at the PIPE Interface
2.1.3. Generating Synthesis Files
2.1.4. Understanding the Files Generated
2.1.5. Understanding Physical Placement of the PCIe IP Core
2.1.6. Compiling the Design in the Quartus® Prime Software
4.1. Arria V Hard IP for PCI Express with Avalon-ST Interface to the Application Layer
4.2. Clock Signals
4.3. Reset Signals
4.4. Hard IP Status
4.5. Error Signals
4.6. ECRC Forwarding
4.7. Interrupts for Endpoints
4.8. Interrupts for Root Ports
4.9. Completion Side Band Signals
4.10. Transaction Layer Configuration Space Signals
4.11. LMI Signals
4.12. Power Management Signals
4.13. Physical Layer Interface Signals
5.1. Correspondence between Configuration Space Registers and the PCIe Specification
5.2. Type 0 Configuration Space Registers
5.3. Type 1 Configuration Space Registers
5.4. PCI Express Capability Structures
5.5. Intel-Defined VSEC Registers
5.6. CvP Registers
5.7. Uncorrectable Internal Error Mask Register
5.8. Uncorrectable Internal Error Status Register
5.9. Correctable Internal Error Mask Register
5.10. Correctable Internal Error Status Register
15.6.1. ebfm_barwr Procedure
15.6.2. ebfm_barwr_imm Procedure
15.6.3. ebfm_barrd_wait Procedure
15.6.4. ebfm_barrd_nowt Procedure
15.6.5. ebfm_cfgwr_imm_wait Procedure
15.6.6. ebfm_cfgwr_imm_nowt Procedure
15.6.7. ebfm_cfgrd_wait Procedure
15.6.8. ebfm_cfgrd_nowt Procedure
15.6.9. BFM Configuration Procedures
15.6.10. BFM Shared Memory Access Procedures
15.6.11. BFM Log and Message Procedures
15.6.12. Verilog HDL Formatting Functions
15.7.1. Changing Between Serial and PIPE Simulation
15.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants
15.7.3. Viewing the Important PIPE Interface Signals
15.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations
15.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
15.7.6. Changing between the Hard and Soft Reset Controller
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2.1.2. Simulating the Example Design
- Start your simulation tool. This example uses the ModelSim® software.
- From the ModelSim transcript window, in the testbench directory type the following commands:
- do msim_setup.tcl
- ld_debug (This command compiles all design files and elaborates the top‑level design without any optimization.)
- run -all
The simulation includes the following stages:
- Link training
- Configuration
- DMA reads and writes
- Root Port to Endpoint memory reads and writes
Disabling Scrambling for Gen1 and Gen2 to Interpret TLPs at the PIPE Interface
- Go to <project_directory/<variant>/testbench/<variant>_tb/simulation/submodules/.
- Open altpcietb_bfm_top_rp.v.
- Locate the declaration of test_in[2:1]. Set test_in[2] = 1 and test_in[1] = 0. Changing test_in[2] = 1 disables data scrambling on the PIPE interface.
- Save altpcietb_bfm_top_rp.v.