Visible to Intel only — GUID: nik1410564847635
Ixiasoft
Visible to Intel only — GUID: nik1410564847635
Ixiasoft
4.1.1.3. Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface
The following figure shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs for TLPs with a three dword header and qword aligned addresses. The assertion of rx_st_empty in a rx_st_eop cycle, indicates valid data on the lower 64 bits of rx_st _data.
The following figure shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs for TLPs with a 3 dword header and non-qword aligned addresses. In this case, bits[127:96] represent Data0 because address[2] in the TLP header is set. The assertion of rx_st_empty in a rx_st_eop cycle indicates valid data on the lower 64 bits of rx_st_data.
The following figure shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs for a four dword header with non-qword aligned addresses. In this example, rx_st_empty is low because the data is valid for all 128 bits in the rx_st_eop cycle.
The following figure shows the mapping of 128-bit Avalon-ST RX packets to PCI Express TLPs for a four dword header with qword aligned addresses. In this example, rx_st_empty is low because data is valid for all 128-bits in the rx_st_eop cycle.
The following figure illustrates the timing of the RX interface when the Application Layer backpressures the Hard IP by deasserting rx_st_ready. The rx_st_valid signal deasserts within three cycles after rx_st_ready is deasserted. In this example, rx_st_valid is deasserted in the next cycle. rx_st_data is held until the Application Layer is able to accept it.
The following figure illustrates back‑to‑back transmission on the 128‑bit Avalon‑ST RX interface with no idle cycles between the assertion of rx_st_eop and rx_st_sop.
The following figure illustrates back‑to‑back transmission on the 128‑bit Avalon‑ST RX interface with no idle cycles between the assertion of rx_st_eop and rx_st_sop.
The following figure illustrates a two‑cycle packet with valid data in the lower qword (rx_st_data[63:0]) and a one‑cycle packet where the rx_st_sop and rx_st_eop occur in the same cycle.