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1. Datasheet
2. Getting Started with the Arria V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Interrupts
7. Error Handling
8. IP Core Architecture
9. Transaction Layer Protocol (TLP) Details
10. Throughput Optimization
11. Design Implementation
12. Additional Features
13. Hard IP Reconfiguration
14. Transceiver PHY IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Document Revision History
1.1. Arria V Avalon-ST Interface for PCIe Datasheet
1.2. Features
1.3. Release Information
1.4. Device Family Support
1.5. Configurations
1.6. Example Designs
1.7. Debug Features
1.8. IP Core Verification
1.9. Performance and Resource Utilization
1.10. Recommended Speed Grades
1.11. Creating a Design for PCI Express
4.1. Arria V Hard IP for PCI Express with Avalon-ST Interface to the Application Layer
4.2. Clock Signals
4.3. Reset Signals
4.4. Hard IP Status
4.5. Error Signals
4.6. ECRC Forwarding
4.7. Interrupts for Endpoints
4.8. Interrupts for Root Ports
4.9. Completion Side Band Signals
4.10. Transaction Layer Configuration Space Signals
4.11. LMI Signals
4.12. Power Management Signals
4.13. Physical Layer Interface Signals
5.1. Correspondence between Configuration Space Registers and the PCIe Specification
5.2. Type 0 Configuration Space Registers
5.3. Type 1 Configuration Space Registers
5.4. PCI Express Capability Structures
5.5. Intel-Defined VSEC Registers
5.6. CvP Registers
5.7. Uncorrectable Internal Error Mask Register
5.8. Uncorrectable Internal Error Status Register
5.9. Correctable Internal Error Mask Register
5.10. Correctable Internal Error Status Register
15.6.1. ebfm_barwr Procedure
15.6.2. ebfm_barwr_imm Procedure
15.6.3. ebfm_barrd_wait Procedure
15.6.4. ebfm_barrd_nowt Procedure
15.6.5. ebfm_cfgwr_imm_wait Procedure
15.6.6. ebfm_cfgwr_imm_nowt Procedure
15.6.7. ebfm_cfgrd_wait Procedure
15.6.8. ebfm_cfgrd_nowt Procedure
15.6.9. BFM Configuration Procedures
15.6.10. BFM Shared Memory Access Procedures
15.6.11. BFM Log and Message Procedures
15.6.12. Verilog HDL Formatting Functions
15.7.1. Changing Between Serial and PIPE Simulation
15.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants
15.7.3. Viewing the Important PIPE Interface Signals
15.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations
15.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
15.7.6. Changing between the Hard and Soft Reset Controller
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11.1. Making Analog QSF Assignments Using the Assignment Editor
You specify the analog parameters using the Quartus® Prime Assignment Editor, the Pin Planner, or through the Quartus® Prime Settings File .(qsf).
Data Rate | VCCR_GXB and VCCT_GXB | VCCA_GXB |
---|---|---|
Arria® V GX: Gen1 and Gen2 | 1.1 V | 2.5 V |
Arria® V GT: Gen1 and Gen2 | 1.2 V | 2.5 V |
The Quartus® Prime software provides default values for analog parameters. You can change the defaults using the Assignment Editor or the Pin Planner. You can also edit your .qsf directly or by typing commands in the Quartus® Prime Tcl Console.
The following example shows how to change the value of the voltages required:
- On the Assignments menu, select Assignment Editor. The Assignment Editor appears.
- Complete the following steps for each pin requiring the VCCR_GXB and V CCT_GXB voltage:
- Double-click in the Assignment Name column and scroll to the bottom of the available assignments.
- Select VCCR_GXB/VCCT_GXB Voltage.
- In the Value column, select 1_1V from the list.
- Complete the following steps for each pin requiring the VCCA_GXB voltage:
- Double-click in the Assignment Name column and scroll to the bottom of the available assignments.
- Select VCCA_GXB Voltage.
- In the Value column, select 3_0V from the list.
The Quartus® Prime software adds these instance assignments commands to the .qsf file for your project.
You can also enter these commands at the Quartus® Prime Tcl Console. For example, the following command sets the XCVR_VCCR_VCCT_VOLTAGE to 1.0 V for the pin specified:
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V to “pin”