AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

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ID 683720
Date 9/01/2018
Public
Document Table of Contents
Document Table of Contents x
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification x
About the Functional Safety Separation Flow Work Flows Functional Safety Separation of a Motor Control Design Example Appendix A: Terminology Appendix B: Design Checklist Document Revision History for AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
Work Flows x
Design Creation Flow Design Modification Flow
Functional Safety Separation of a Motor Control Design Example x
Design Considerations Design Creation Flow Using the Design Modification Flow
Design Considerations x
About Safety IP Partitions and LogicLock Regions Assigning I/O Pins Clocks, PLLs and Resets Routing Across Safety IP Partitions
Design Creation Flow x
Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
Using the Intel® Quartus® Prime Incremental Compilation x
Creating a Partition for the FOC Fixed-Point Component Creating a LogicLock Region for the FOC Fixed-Point Component
Generating Safety IP Bitstream Files x
Generating Complete FPGA Bitstream File
Using the Design Modification Flow x
Changing Nonsafety IP - Changing FOC Algorithm Parameter Adding New Features to Nonsafety IP Importing Safety IP Partition
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

Removing Precomiled Netlists

If you are using the design creation flow, you should remove any previously compiled netlists for safety IP partitions before recompiling the design. You must remove precompiled netlists, otherwise:
  • If the source code changes for the safety IP and you turn on the Ignore changes in source files and strictly use the specified netlist, if available design partition property, the Intel® Quartus® Primesoftware uses the previous netlist and does not include the changes in the safety IP.
  • If the source code does not change for the safety IP, you may see a no-fit error. The safety IP partition uses the design modification flow and restricts the place and route unnecessarily.
  1. Right-click on the safety IP partition in the Design Partitions window,
  2. Select Advanced > Delete Netlists.
The Intel® Quartus® Prime software then recompiles the safety IP partitions from the source files and the fitter can reroute and place the safety IP partition.
Level Two Title