AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

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ID 683720
Date 9/01/2018
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Document Table of Contents
Document Table of Contents x
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification x
About the Functional Safety Separation Flow Work Flows Functional Safety Separation of a Motor Control Design Example Appendix A: Terminology Appendix B: Design Checklist Document Revision History for AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
Work Flows x
Design Creation Flow Design Modification Flow
Functional Safety Separation of a Motor Control Design Example x
Design Considerations Design Creation Flow Using the Design Modification Flow
Design Considerations x
About Safety IP Partitions and LogicLock Regions Assigning I/O Pins Clocks, PLLs and Resets Routing Across Safety IP Partitions
Design Creation Flow x
Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
Using the Intel® Quartus® Prime Incremental Compilation x
Creating a Partition for the FOC Fixed-Point Component Creating a LogicLock Region for the FOC Fixed-Point Component
Generating Safety IP Bitstream Files x
Generating Complete FPGA Bitstream File
Using the Design Modification Flow x
Changing Nonsafety IP - Changing FOC Algorithm Parameter Adding New Features to Nonsafety IP Importing Safety IP Partition
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

Design Hierarchy and safety IP partitions

The first stage of the design creation flow is to define the design hierarchy and safety IP partitions. You should implement every safety related IP in your design in a partition(s) so the safety IP is protected from recompilation.

To demonstrate the design flow for the motor control system example, Intel considers the following IP is safety related:

  • DC Link Monitor, PLL, associated clocking structure and IO pins
  • The six-channel PWM in the drive channel 0 subsystem
  • FOC subsystem (nonsafety IP)
Figure 10. The Main Entities in the Design Hierarchy and the Logical Design Partitions


The design hierarchy allows design flexibility and is suitable for logical separation of the safety components in this example. Intel groups together the drive channel peripherals , independent of the FOC algorithm and the Nios II processor. This design can support many drive axes, with only a single instance of the FOC algorithm or Nios II processor.

This design specifies two safety related IP as design partitions, and one nonsafety IP partition. Using nonsafety IP partitions in the functional safety separation flow is optional.

Intel achieves strict preservation for safety IP partitions using the global .qsf assignment PARTITION_ENABLE_STRICT_PRESERVATION.

set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION <ON/OFF> - section_id < partition_name >

The assignment exhibits the following properties

  • When any partition has the assignment value ON, the Intel® Quartus® Prime software enables the safety and nonsafety separation flow
  • A partition default assignment value is OFF (nonsafety IP). In other words, when a partition has the assignment value OFF, it is equivalent to not having the PARTITION_ENABLE_STRICT_PRESERVATION assignment and specifies that the partition is defined as nonsafety IP
  • You may only assign partitions and I/O pins to safety IP.
  • A partition assigned to safety IP may contain safe logic only. If you assign a parent partition to a safety IP, consider all its child partitions as part of the same safety IP.
  • A design may contain several safety IP paritions. All the partitions containing logic that implements a single safety IP functionality should belong with the same top-level parent partition.
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