AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

Download PDF
ID 683720
Date 9/01/2018
Public
Document Table of Contents
Document Table of Contents x
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification x
About the Functional Safety Separation Flow Work Flows Functional Safety Separation of a Motor Control Design Example Appendix A: Terminology Appendix B: Design Checklist Document Revision History for AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
Work Flows x
Design Creation Flow Design Modification Flow
Functional Safety Separation of a Motor Control Design Example x
Design Considerations Design Creation Flow Using the Design Modification Flow
Design Considerations x
About Safety IP Partitions and LogicLock Regions Assigning I/O Pins Clocks, PLLs and Resets Routing Across Safety IP Partitions
Design Creation Flow x
Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
Using the Intel® Quartus® Prime Incremental Compilation x
Creating a Partition for the FOC Fixed-Point Component Creating a LogicLock Region for the FOC Fixed-Point Component
Generating Safety IP Bitstream Files x
Generating Complete FPGA Bitstream File
Using the Design Modification Flow x
Changing Nonsafety IP - Changing FOC Algorithm Parameter Adding New Features to Nonsafety IP Importing Safety IP Partition
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

Generating Safety IP Bitstream Files

The design modification flow requires a safety IP bitstream file, known as a partially preserved bitstream. The separate safety IP partitioning verification tool reads the partially preserved bitstream file to verify that no change occurs to the state of safety IP regions ( i.e. whether the safety region is unchanged) or other relevant device level configuration options.
Note:

Run any command-lines below from a Nios II 17.0 Command Shell with the current directory set to the Quartus Prime project output_files directory.

  1. Post process the bitstream file (.sof) generated by the Intel® Quartus® Prime assembler, to create the partially preserved bitstream file using the following command 
    quartus_cpf --genppb <partitionname>.psm  <projectname>.sof <partitonname>.rbf.ppb
quartus_cpf -c <partitionname>.psm  <partitonname>.rbf.ppb
    The following commands generate the partially preserved bitstream for two safety IP partitions. 
    quartus_cpf --genppb DOC_Single_Axis_FE2H_CVE_DOC_Safe_PLL_DC_Link-doc_safe_pll_dc_link.psm  DOC_top_FE2H_CVE.sof  DOC_Single_Axis_FE2H_CVE_DOC_Safe_PLL_DC_Link-doc_safe_pll_dc_link.rbf.ppb

quartus_cpf -c DOC_Single_Axis_FE2H_CVE_DOC_Safe_PLL_DC_Link-doc_safe_pll_dc_link.psm   DOC_Single_Axis_FE2H_CVE_DOC_Safe_PLL_DC_Link-doc_safe_pll_dc_link.rbf.ppb

quartus_cpf --genppb ssg_emb_pwm-doc_pwm.psm  DOC_top_FE2H_CVE.sof ssg_emb_pwm-doc_pwm.rbf.ppb

quartus_cpf -c ssg_emb_pwm-doc_pwm.psm  ssg_emb_pwm-doc_pwm.rbf.ppb
    During partially preserved bitstream file generation, the Intel® Quartus® Prime software generates an additional checksum file <partitionname>.md5.sign.
  2. Archive the generated .psm, .ppb and .md5.sign files for use later in the design modification flow. For this example, create a design creation flow directory in the output_files directory and copy the following files to it:
    • DOC_Single_Axis_FE2H_CVE_DOC_Safe_PLL_DC_Link-doc_safe_pll_dc_link.md5.sign
    • DOC_Single_Axis_FE2H_CVE_DOC_Safe_PLL_DC_Link-doc_safe_pll_dc_link.psm
    • DOC_Single_Axis_FE2H_CVE_DOC_Safe_PLL_DC_Link-doc_safe_pll_dc_link.rbf.ppb
    • ssg_emb_pwm-doc_pwm.md5.sign
    • ssg_emb_pwm-doc_pwm.psm
    • ssg_emb_pwm-doc_pwm.rbf.ppb
    • Quartus settings (.qpf ,.qsf)
    • HDL Source code, IP, Qsys project (design specific)
    • Exported partition netlists (for safe and other post-fit partitions) (.qxp)
    • Programming file (.sof)
    • Additional safety IP bitstream files (.psm, .ppb, ,md5.sign)
    Note: The Intel® Quartus® Prime archiver does not include all these file types by default. You must ensure all necessary files are archived.
    Note: When unarchiving, use a commonly available MD5 checksum utility (e.g. md5sum shipped with Cygwin in the ) to regerenate the MD5 checksum of the .rbf.ppb and .psm files and compare against those stored in the md5.sign file to check the files for any corruption.
Level Two Title