AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

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ID 683720
Date 9/01/2018
Public
Document Table of Contents
Document Table of Contents x
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification x
About the Functional Safety Separation Flow Work Flows Functional Safety Separation of a Motor Control Design Example Appendix A: Terminology Appendix B: Design Checklist Document Revision History for AN 704: FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification
Work Flows x
Design Creation Flow Design Modification Flow
Functional Safety Separation of a Motor Control Design Example x
Design Considerations Design Creation Flow Using the Design Modification Flow
Design Considerations x
About Safety IP Partitions and LogicLock Regions Assigning I/O Pins Clocks, PLLs and Resets Routing Across Safety IP Partitions
Design Creation Flow x
Design Hierarchy and safety IP partitions Preparing the Design Example in the Intel® Quartus® Prime Software DC Link Monitor safety IP partition Creating a Safety IP partition for the DC Link Monitor and PLL Subsystem Component Creating a Safety IP partition for the PWM Interface Component Creating a Safety IP LogicLock Region for the DC Link Monitor Creating a LogicLock Region for the PWM Interface Creating a Fixed Size and Origin for a LogicLock Region Removing Precomiled Netlists Using the Intel® Quartus® Prime Incremental Compilation Compiling the Design The Fitter Report Exporting Safety IP Partition Generating Safety IP Bitstream Files
Using the Intel® Quartus® Prime Incremental Compilation x
Creating a Partition for the FOC Fixed-Point Component Creating a LogicLock Region for the FOC Fixed-Point Component
Generating Safety IP Bitstream Files x
Generating Complete FPGA Bitstream File
Using the Design Modification Flow x
Changing Nonsafety IP - Changing FOC Algorithm Parameter Adding New Features to Nonsafety IP Importing Safety IP Partition
FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

FPGA-based Safety Separation Design Flow for Rapid Functional Safety Certification

This design flow significantly reduces the certification efforts for the lifetime of an FPGA-based industrial system containing both safety critical and nonsafety critical components.

This application note describes how to use the design flow with a motor control system design example.

Industrial machinery manufacturers throughout the world experience the continuous pressure to reduce system cost, extend performance and efficiency, and deliver to ever reduced timescales. For products in safety critical environments, designers also strive to ensure safe behavior with compliance to IEC 61508: Functional Safety of electrical/electronic/programmable electronic safety-related systems and ISO 26262: Road vehicles - Functional safety.

FPGA-based systems provide designer with design flexibility performance scalability, and integration options. The TÜV Rheinland approved safety separation design flow retains these FPGA benefits and completely removes the need for a full design certification (when you don't change safety critical regions in a single FPGA device).

You can create safety and non-safety regions (or partitions) on a single Cyclone® IV, Cyclone V or Intel® MAX® 10 device. When you only change non-safety regions, the safety areas are fully preserved. The design flow provides the evidence that the placement and routing in the safety regions are identical to a previous hardware compilation. Then you should validate the FPGA design to ensure that the modified non-safety regions of the FPGA perform correctly with the safety regions. This validation may include functional tests of the safety regions.

Level Two Title