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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 5 E-Series Devices
3. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 M-Series Devices
4. PHY Lite for Parallel Interfaces Intel® FPGA IP for Agilex™ 7 F-Series and I-Series Devices
5. PHY Lite for Parallel Interfaces Intel® FPGA IP for Stratix® 10 Devices
6. PHY Lite for Parallel Interfaces Intel® FPGA IP for Arria® 10 and Cyclone® 10 GX Devices
7. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
8. Document Revision History for the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
6.5.6.4.1. Timing Closure: Dynamic Reconfiguration
6.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
6.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
6.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
6.5.6.4.5. I/O Timing Violation
6.5.6.4.6. Internal FPGA Path Timing Violation
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6.4.2.2. Manual Insertion of OCT Block
You may also instantiate the OCT Intel® FPGA IP separately in your project and connect the termination ports to the PHY Lite for Parallel Interfaces Intel® FPGA IP.
- Expose the PHY Lite for Parallel Interfaces Intel® FPGA IP termination ports by disable Use Default OCT Values.
- Select the available OCT values in the Input OCT Value parameter. This displays the Expose termination ports parameter.
Note: For supported input and output OCT values, refer to the I/O Standards topic.
- Select Expose termination ports to expose the termination ports in the IP.
- Connect the termination ports to a OCT Intel FPGA IP either in power-up or user mode.
Figure 163. RTL View of PHY Lite for Parallel Interfaces Intel® FPGA IP Interfacing with OCT Intel® FPGA IP in User Mode
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