AN 847: Signal Tap Tutorial with Design Block Reuse: for Intel® Arria® 10 FPGA Development Board

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ID 683712
Date 12/21/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Core Partition Reuse Debug—Developer 3. Core Partition Reuse Debug—Consumer 4. Root Partition Reuse Debug—Developer 5. Root Partition Reuse Debug—Consumer 6. AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board Archives 7. Document Revision History for AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board
1. Introduction x
1.1. Tutorial Software and Hardware 1.2. Tutorial Files 1.3. Signal Tap with Core Partition Reuse 1.4. Signal Tap with Root Partition Reuse
2. Core Partition Reuse Debug—Developer x
2.1. Step 1: Creating a Core Partition 2.2. Step 2: Creating Partition Boundary Ports 2.3. Step 3: Compiling and Checking Debug Nodes 2.4. Step 4: Exporting the Core Partition and Creating the Black Box File 2.5. Step 5: Copying Files to Consumer Project 2.6. Step 6: Creating a Signal Tap File (Optional) 2.7. Step 7: Programming the Device and Verifying the Hardware 2.8. Step 8: Verifying Hardware with Signal Tap
3. Core Partition Reuse Debug—Consumer x
3.1. Step 1: Adding Files and Running Synthesis 3.2. Step 2: Creating a Signal Tap File 3.3. Step 3: Creating a Partition for blinking_led_top 3.4. Step 4: Compiling the Design and Verifying Debug Nodes 3.5. Step 5: Programming the Device and Verifying the Hardware 3.6. Step 6: Verifying Hardware with Signal Tap
4. Root Partition Reuse Debug—Developer x
4.1. Step 1: Creating a Reserved Core Partition and Defining a Logic Lock Region 4.2. Step 2: Generating and Instantiating SLD JTAG Bridge Agent in the Root Partition 4.3. Step 3: Generating and Instantiating the SLD JTAG Bridge Host 4.4. Step 4: Generating HDL Instance of Signal Tap 4.5. Step 5: Compiling Export Root Partition and Copying Files to Consumer Project 4.6. Step 6: Programming the Device and Verifying the Hardware 4.7. Step 7: Generating a Signal Tap File for the Root Partition 4.8. Step 8: Verifying the Hardware with Signal Tap
5. Root Partition Reuse Debug—Consumer x
5.1. Step 1: Adding Files to Customer Project 5.2. Step 2: Generating and Instantiating SLD JTAG Bridge Host in Reserved Core Partition 5.3. Step 3: Synthesizing, Creating Signal Tap File, and Compiling 5.4. Step 4: Programming the Device and Verifying the Hardware 5.5. Step 5: Verifying the Hardware of Reserved Core Partition with Signal Tap 5.6. Step 6: Verifying Hardware of Root Partition with Signal Tap
1. Introduction
2. Core Partition Reuse Debug—Developer
3. Core Partition Reuse Debug—Consumer
4. Root Partition Reuse Debug—Developer
5. Root Partition Reuse Debug—Consumer
6. AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board Archives
7. Document Revision History for AN 847: Signal Tap Tutorial with Design Block Reuse for Intel® Arria® 10 FPGA Development Board

4.3. Step 3: Generating and Instantiating the SLD JTAG Bridge Host

  1. From the IP Catalog (Tools > IP Catalog), select and generate the SLD JTAG Bridge Host Intel® FPGA IP . Set the name as debug_host.
    For details about generating the SLD JTAG Bridge Host Intel® FPGA IP, refer to the Intel® Quartus® Prime Pro Edition User Guide: Debug Tools .
  2. Open the blinking_led_top.sv file, uncomment the lines 25 to 30 and 41 to 48, and save the file.
    This action instantiates the SLD JTAG Bridge Host in the Reserved Core partition, connecting the debug fabric to the parent partition.

    Lines 25 to 30: 

    //		input wire tck (tck),		 // connect_to_bridge_host .tck
//		input wire tms (tms),		 // .tms
//		input wire tdi (tdi),	 	// .tdi
//		input wire vir_tdi (vir_tdi), // .vir_tdi
//		input wire ena (ena),		 // .ena
//		output wire tdo (tdo)		 // .tdo

    Lines 41 to 48: 

    //   debug_host debug_host_inst ( 
//      .tck (tck),   //input, width=1, connect_to_bridge_host .tck
//      .tms (tms),   //input, width=1, .tms
//      .tdi (tdi),   //input, width=1, .tdi
//      .vir_tdi (vir_tdi), //input, width=1, .vir_tdi
//      .ena (ena),    //input, width=1, .ena
//      .tdo ()        //output, width=1, .tdo
//      );
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