OCT Intel® FPGA IP User Guide

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ID 683708
Date 7/03/2019
Public
Document Table of Contents
Document Table of Contents x
OCT Intel® FPGA IP User Guide
OCT Intel® FPGA IP User Guide x
OCT Intel® FPGA IP Features OCT Intel® FPGA IP Overview OCT Intel® FPGA IP Functional Description OCT Intel® FPGA IP Design Example OCT Intel® FPGA IP References OCT Intel® FPGA IP User Guide Archives Document Revision History for OCT Intel® FPGA IP User Guide
OCT Intel® FPGA IP Overview x
RZQ Pin OCT Block OCT Logic
OCT Intel® FPGA IP Functional Description x
Power-Up Mode Interfaces User Mode OCT
User Mode OCT x
Core FSM
OCT Intel® FPGA IP Design Example x
Generating the Intel® Quartus® Prime Design Example
OCT Intel® FPGA IP References x
OCT Intel® FPGA IP Parameter Settings OCT Intel® FPGA IP Signals QSF Assignments IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTOCT IP to the OCT Intel® FPGA IP
OCT Intel® FPGA IP User Guide

OCT Intel® FPGA IP Design Example

The OCT IP can generate a design example that matches the same configuration chosen for the IP.

The design example is a simple design that does not target any specific application. You can use the design example as a reference on how to instantiate the IP.

To generate the design example files, turn on the Generate Example Design option in the Generation dialog box during IP generation.

Note: The OCT IP does not support VHDL generation.
  • The software generates the <instance>_example_design directory along with the IP, where <instance> is the name of your IP.
  • The <instance>_example_design directory contains the make_qii_design.tcl scripts.
Note: The .qsys files are for internal use during design example generation only. You cannot edit the files.
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