OCT Intel® FPGA IP User Guide

Download PDF
ID 683708
Date 7/03/2019
Public
Document Table of Contents
Document Table of Contents x
OCT Intel® FPGA IP User Guide
OCT Intel® FPGA IP User Guide x
OCT Intel® FPGA IP Features OCT Intel® FPGA IP Overview OCT Intel® FPGA IP Functional Description OCT Intel® FPGA IP Design Example OCT Intel® FPGA IP References OCT Intel® FPGA IP User Guide Archives Document Revision History for OCT Intel® FPGA IP User Guide
OCT Intel® FPGA IP Overview x
RZQ Pin OCT Block OCT Logic
OCT Intel® FPGA IP Functional Description x
Power-Up Mode Interfaces User Mode OCT
User Mode OCT x
Core FSM
OCT Intel® FPGA IP Design Example x
Generating the Intel® Quartus® Prime Design Example
OCT Intel® FPGA IP References x
OCT Intel® FPGA IP Parameter Settings OCT Intel® FPGA IP Signals QSF Assignments IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTOCT IP to the OCT Intel® FPGA IP
OCT Intel® FPGA IP User Guide

User Mode OCT

User mode OCT operates the same way as power-up OCT mode, with the addition of user controllability.
Figure 6. FSM SignalsThis figure shows a finite state machine (FSM) in the core controls the dedicated user signals on the OCT block. The FSM ensures that the OCT block calibrates or sends controlling code words as per your request.


The Fitter does not infer a user-mode OCT. If you want your OCT block to use the user mode OCT feature, you must generate the OCT IP. However, because of hardware limitations, you can only use one OCT IP in user mode OCT in your design.

Note: A single OCT IP can control up to 12 OCT blocks.

The FSM provides the following signals:

  • clock
  • reset
  • s2pload
  • calibration_busy
  • calibration_shift_busy
  • calibration_request
Note: These signals are only available in user-mode and not power-up mode.
Related Information
Level Two Title