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Ixiasoft
OCT Intel® FPGA IP Overview
Figure 1. OCT IP Top-Level DiagramThis figure shows the top-level diagram of the OCT IP.
Component | Description |
---|---|
RZQ pin |
|
OCT block | Generates and sends calibration code words to the I/O buffer blocks. |
OCT logic | Receives the calibration code words serially from the OCT block and sends the calibration code words in parallel to the buffers. |