OCT Intel® FPGA IP User Guide

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ID 683708
Date 7/03/2019
Public
Document Table of Contents
Document Table of Contents x
OCT Intel® FPGA IP User Guide
OCT Intel® FPGA IP User Guide x
OCT Intel® FPGA IP Features OCT Intel® FPGA IP Overview OCT Intel® FPGA IP Functional Description OCT Intel® FPGA IP Design Example OCT Intel® FPGA IP References OCT Intel® FPGA IP User Guide Archives Document Revision History for OCT Intel® FPGA IP User Guide
OCT Intel® FPGA IP Overview x
RZQ Pin OCT Block OCT Logic
OCT Intel® FPGA IP Functional Description x
Power-Up Mode Interfaces User Mode OCT
User Mode OCT x
Core FSM
OCT Intel® FPGA IP Design Example x
Generating the Intel® Quartus® Prime Design Example
OCT Intel® FPGA IP References x
OCT Intel® FPGA IP Parameter Settings OCT Intel® FPGA IP Signals QSF Assignments IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTOCT IP to the OCT Intel® FPGA IP
OCT Intel® FPGA IP User Guide

QSF Assignments

Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices have the following termination-related Intel® Quartus® Prime settings file (.qsf) assignments:

  • INPUT_TERMINATION
  • OUTPUT_TERMINATION
  • TERMINATION_CONTROL_BLOCK
  • RZQ_GROUP
Table 5.  QSF Assignments
QSF Assignment Details
INPUT_TERMINATION

OUTPUT_TERMINATION

The input/output termination assignment specifies the termination value in ohm on the pin in question.

Example: 

set_instance_assignment -name INPUT_TERMINATION <value> -to <pin name>
set_instance_assignment -name OUTPUT_TERMINATION <value> -to <pin name>

To enable the series/parallel termination ports, include these assignments, which specify the series and parallel termination values for the pins.

Make sure to connect the seriesterminationcontrol and parallelterminationcontrol ports from the OCT Intel® FPGA IP to the GPIO Intel® FPGA IP.

Example: 
set_instance_assignment -name INPUT_TERMINATION "PARALLEL <VALUE> OHM WITH CALIBRATION" -to <pin>
set_instance_assignment -name OUTPUT_TERMINATION "SERIES <VALUE> OHM WITH CALIBRATION" -to <pin>
TERMINATION_CONTROL_BLOCK

Directs the Fitter to make the proper connection from the desired OCT block to the specified pins. This assignment is useful when I/O buffers are not explicitly instantiated and you need to associate the pins with a specific OCT block.

Example:

set_instance_assignment -name TERMINATION_CONTROL_BLOCK <desired OCT BLK> -to <pin name>
RZQ_GROUP

This assignment is supported in Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices only. This assignment creates an OCT IP without modifying the RTL.

The Fitter searches for the rzq pin name in the netlist. If the pin does not exist, the Fitter creates the pin name along with the OCT IP and its corresponding connections. This allows you to create a group of pins to be calibrated by an existing or non-existing OCT and the Fitter ensures the legality of the design.

Example:

set_instance_assignment -name RZQ_GROUP <rzq pin name> -to <pin name>

Termination can exist on input and output buffers, and sometimes simultaneously.

There are two methods to associate pin groups with an OCT block:

  • Use a .qsf assignment to indicate which pin (bus) is associated with which OCT block. You can use the TERMINATION_CONTROL_BLOCK or RZQ_GROUPassignment. The former assignment associates a pin with an OCT instantiated in the RTL while the latter associates the pin with a newly created OCT without modifying the RTL.
  • Instantiate the I/O buffer primitives at the top level and connect them to the appropriate OCT blocks.
Note: All I/O banks with the same VCCIO can share one OCT block even if that particular I/O bank has its own OCT block. You can connect any number of I/O pins that support calibrated termination to an OCT block. Ensure that you connect I/Os with compatible configuration to an OCT block. You must also ensure that the OCT block and its corresponding I/Os have the same VCCIO and series or parallel termination values. With these settings, the Fitter places the I/Os and OCT block in the same column. The Intel® Quartus® Prime software generates warning messages if there is no pin connected to the block.
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