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Ixiasoft
Introduction
System-Level Debugging Infrastructure
Virtual JTAG Interface Description
Run-Time Communication
Instantiating the Virtual JTAG Intel® FPGA IP Core
Simulation Support
Compiling the Design
SLD_NODE Discovery and Enumeration
Capturing the Virtual IR Instruction Register
AHDL Function Prototype
VHDL Component Declaration
VHDL LIBRARY-USE Declaration
Design Example: TAP Controller State Machine
Design Example: Modifying the DCFIFO Contents at Runtime
Design Example: Offloading Hardwired Revision Information
Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Visible to Intel only — GUID: bhc1411109294872
Ixiasoft
Introduction
The Virtual JTAG Intel® FPGA IP core allows you to create your own software solution for monitoring, updating, and debugging designs through the JTAG port without using I/O pins on the device, and is one feature in the On‑Chip Debugging Tool Suite. The Quartus® Prime software or JTAG control host identifies each instance of this IP core by a unique index. Each IP core instance functions in a flow that resembles the JTAG operation of a device. The logic that uses this interface must maintain the continuity of the JTAG chain on behalf the PLD device when this instance becomes active.
With the Virtual JTAG Intel® FPGA IP core you can build your design for efficient, fast, and productive debugging solutions. Debugging solutions can be part of an evaluation test where you use other logic analyzers to debug your design, or as part of a production test where you do not have a host running an embedded logic analyzer. In addition to debugging features, you can use the Virtual JTAG Intel® FPGA IP core to provide a single channel or multiple serial channels through the JTAG port of the device. You can use serial channels in applications to capture data or to force data to various parts of your logic.
Each feature in the On‑Chip Debugging Tool Suite leverages on-chip resources to achieve real time visibility to the logic under test. During runtime, each tool shares the JTAG connection to transmit collected test data to the Quartus® Prime software for analysis. The tool set consists of a set of GUIs, IP core intellectual property (IP) cores, and Tcl application programming interfaces (APIs). The GUIs provide the configuration of test signals and the visualization of data captured during debugging. The Tcl scripting interface provides automation during runtime.
The Virtual JTAG Intel® FPGA IP core provides you direct access to the JTAG control signals routed to the FPGA core logic, which gives you a fine granularity of control over the JTAG resource and opens up the JTAG resource as a general‑purpose serial communication interface. A complete Tcl API is available for sending and receiving transactions into your device during runtime. Because the JTAG pins are readily accessible during runtime, this IP core enables an easy way to customize a JTAG scan chain internal to the device, which you can then use to create debugging applications.
Examples of debugging applications include induced trigger conditions evaluated by a Signal Tap logic analyzer by exercising test signals connected to the analyzer instance, a replacement for a front panel interface during the prototyping phase of the design, or inserted test vectors for exercising the design under test.
The infrastructure is an extension of the JTAG protocol for use with Intel® ‑specific applications and user applications, such as the Signal Tap logic analyzer.