Virtual JTAG Intel® FPGA IP Core User Guide

Download PDF
ID 683705
Date 8/12/2021
Public
Document Table of Contents
Document Table of Contents x
Virtual JTAG Intel® FPGA IP Core User Guide
Virtual JTAG Intel® FPGA IP Core User Guide x
Introduction System-Level Debugging Infrastructure Virtual JTAG Interface Description Run-Time Communication Instantiating the Virtual JTAG Intel® FPGA IP Core Simulation Support Compiling the Design SLD_NODE Discovery and Enumeration Capturing the Virtual IR Instruction Register AHDL Function Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration Design Example: TAP Controller State Machine Design Example: Modifying the DCFIFO Contents at Runtime Design Example: Offloading Hardwired Revision Information Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Introduction x
Installing and Licensing Intel® FPGA IP Cores On-Chip Debugging Tool Suite Applications of the Virtual JTAG Intel® FPGA IP Core JTAG Protocol JTAG Circuitry Architecture
System-Level Debugging Infrastructure x
Transaction Model of the SLD Infrastructure SLD Hub Finite State Machine
Virtual JTAG Interface Description x
Input Ports Output Ports Parameters Design Flow of the Virtual JTAG Intel® FPGA IP Core Simulation Model Run-Time Communication Running a DR Shift Operation Through a Virtual JTAG Chain
Run-Time Communication x
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values Reset Considerations when Using a Custom JTAG Controller
Instantiating the Virtual JTAG Intel® FPGA IP Core x
IP Catalog and Parameter Editor Specifying IP Core Parameters and Options Instantiating Directly in HDL
IP Catalog and Parameter Editor x
The Parameter Editor
Specifying IP Core Parameters and Options x
Files Generated for Intel® FPGA IP Cores (Legacy Parameter Editor)
Compiling the Design x
Third-Party Synthesis Support
SLD_NODE Discovery and Enumeration x
Issuing the HUB_INFO Instruction HUB IP Configuration Register SLD_NODE Info Register
Design Example: Modifying the DCFIFO Contents at Runtime x
Write Logic Read Logic Runtime Communication
Design Example: Offloading Hardwired Revision Information x
Configuring the JTAG User Code Setting
Virtual JTAG Intel® FPGA IP Core User Guide

Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values

The Tcl command examples below show that the no_captured_value option is not set in the Virtual IR/DR shift commands and the underlying JTAG shift commands associated with each. In the VIR shift command, the command returns two device_dr_shift commands.
Virtual IR Shift

device_virtual_ir_shift -instance_index 0 -ir_value 1 \

-no_captured_ir_value -show_equivalent_device_ir_dr_shift

Returns:

Info: Equivalent device ir and dr shift commands

Info: device_ir_shift -ir_value 14

Info: device_dr_shift –length 5 –dr_value 0B –value_in_hex

Info: device_dr_shift -length 5 -dr_value 11 -value_in_hex

Virtual DR Shift

device_virtual_dr_shift -instance_index 0 -length 8 -dr_value \

04 -value_in_hex -show_equivalent_device_ir_dr_shift

Returns:

Info: Equivalent device ir and dr shift commands

Info: device_ir_shift -ir_value 12

Info: device_dr_shift -length 8 -dr_value 04 -value_in_hex

The figure below shows an example of VIR/VDR Shift Commands with captured IR values. DR Scan Shift 1 is the VIR_CAPTURE command, as shown in the figure below. It targets the VIR of the sld_hub. This command is an address cycle to select the active VIR chain to shift after jtag_state_cir is asserted. The HUB_FORCE_IR capture must be issued whenever you capture the VIR from a target SLD node that is different than the current active node. DR Scan Shift 1 targets the SLD hub VIR to force a captured value from Virtual JTAG instance 1 and is shown as the VIR_CAPTURE command. DR Scan Shift 2 targets the VIR of Virtual JTAG instance.

Figure 12. Equivalent Bit Pattern Shifted into Device by VIR/VDR Shift Commands with Captured IR Values
Note: If you use an embedded processor as a controller for the JTAG chain and your Virtual JTAG Intel® FPGA IP core instances, consider using the JAM Standard Test and Programming Language (STAPL). JAM STAPL is an industry‑standard flow‑control‑based language that supports JTAG communication transactions. JAM STAPL is open source, with software downloads and source code available from the Intel® website.
Related Information
Level Two Title