Virtual JTAG Intel® FPGA IP Core User Guide

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ID 683705
Date 8/12/2021
Public
Document Table of Contents
Document Table of Contents x
Virtual JTAG Intel® FPGA IP Core User Guide
Virtual JTAG Intel® FPGA IP Core User Guide x
Introduction System-Level Debugging Infrastructure Virtual JTAG Interface Description Run-Time Communication Instantiating the Virtual JTAG Intel® FPGA IP Core Simulation Support Compiling the Design SLD_NODE Discovery and Enumeration Capturing the Virtual IR Instruction Register AHDL Function Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration Design Example: TAP Controller State Machine Design Example: Modifying the DCFIFO Contents at Runtime Design Example: Offloading Hardwired Revision Information Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Introduction x
Installing and Licensing Intel® FPGA IP Cores On-Chip Debugging Tool Suite Applications of the Virtual JTAG Intel® FPGA IP Core JTAG Protocol JTAG Circuitry Architecture
System-Level Debugging Infrastructure x
Transaction Model of the SLD Infrastructure SLD Hub Finite State Machine
Virtual JTAG Interface Description x
Input Ports Output Ports Parameters Design Flow of the Virtual JTAG Intel® FPGA IP Core Simulation Model Run-Time Communication Running a DR Shift Operation Through a Virtual JTAG Chain
Run-Time Communication x
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values Reset Considerations when Using a Custom JTAG Controller
Instantiating the Virtual JTAG Intel® FPGA IP Core x
IP Catalog and Parameter Editor Specifying IP Core Parameters and Options Instantiating Directly in HDL
IP Catalog and Parameter Editor x
The Parameter Editor
Specifying IP Core Parameters and Options x
Files Generated for Intel® FPGA IP Cores (Legacy Parameter Editor)
Compiling the Design x
Third-Party Synthesis Support
SLD_NODE Discovery and Enumeration x
Issuing the HUB_INFO Instruction HUB IP Configuration Register SLD_NODE Info Register
Design Example: Modifying the DCFIFO Contents at Runtime x
Write Logic Read Logic Runtime Communication
Design Example: Offloading Hardwired Revision Information x
Configuring the JTAG User Code Setting
Virtual JTAG Intel® FPGA IP Core User Guide

Instantiating Directly in HDL

To properly connect the Virtual JTAG Intel® FPGA IP core in your design, follow these basic connection rules:
  • The tck output from the Virtual JTAG Intel® FPGA IP core is the clock used for shifting the data in and out on the TDI and TDO pins.
  • The TMS output of the Virtual JTAG Intel® FPGA IP core reflects the TMS input to the main JTAG circuit.
  • The ir_in output port of the Virtual JTAG Intel® FPGA IP core is the parallel output of the contents that get shifted into the virtual IR of the Virtual JTAG instance. This port is used for decoding logic to select the active virtual DR chain.

The purpose of instantiating a Virtual JTAG instance in this example is to load my_counter through the JTAG port using a software application built with Tcl commands and the quartus_stp executable. In this design, the Virtual JTAG instance is called my_vji. Whenever a Virtual JTAG Intel® FPGA IP core is instantiated in a design, three logic blocks are usually needed: a decode logic block, a TDO logic block, and a Data Register block. The example below combines the Virtual JTAG instance, the decode logic, the TDO logic and the Data Register blocks.

You can use the following Verilog HDL template as a guide for instantiating and connecting various signals of the IP cores in your design. 

module        counter (clock, my_counter);
input         clock;
output [3:0]  my_counter;
reg [3:0]     my_counter;
always @ (posedge clock)
   if (load && e1dr) // decode logic: used to load the counter my_counter
      my_counter <= tmp_reg;
   else
      my_counter <= my_counter + 1;
// Signals and registers declared for VJI instance 
wire tck, tdi;
reg  tdo;
wire cdr, eldr, e2dr, pdr, sdr, udr, uir, cir;
wire [1:0] ir_in;

// Instantiation of VJI
my_vji  VJI_INST(
      .tdo (tdo),
      .tck (tck),
      .tdi (tdi),
      .tms(),
      .ir_in(ir_in),
      .ir_out(),
      .virtual_state_cdr (cdr),
      .virtual_state_e1dr(e1dr),
      .virtual_state_e2dr(e2dr),
      .virtual_state_pdr (pdr),
      .virtual_state_sdr (sdr),
      .virtual_state_udr (udr),
      .virtual_state_uir (uir),
      .virtual_state_cir (cir)
);
// Declaration of data register
reg [3:0] tmp_reg;
// Deocde Logic Block
// Making some decode logic from ir_in output port of VJI
wire load = ir_in[1] && ~ir_in[0];
// Bypass used to maintain the scan chain continuity for
// tdi and tdo ports 

bypass_reg <= tdi;
// Data Register Block
always @ (posedge tck)
   if ( load && sdr )
      tmp_reg <= {tdi, tmp_reg[3:1]};
// tdo Logic Block
always @ (tmp_reg[0] or bypass_reg)
   if(load) 
      tdo <= tmp_reg[0]
   else
      tdo <= bypass_reg;
endmodule

The decode logic is produced by defining a wire load to be active high whenever the IR of the Virtual JTAG Intel® FPGA IP core is 01. The IR scan shift is used to load the data into the IR of the Virtual JTAG Intel® FPGA IP core. The ir_in output port reflects the IR contents.

The Data Register logic contains a 4-bit shift register named tmp_reg. The always blocks shown for the Data Register logic also contain the decode logic consisting of the load and sdr signals. The sdr signal is the output of the Virtual JTAG Intel® FPGA IP core that is asserted high during a DR scan shift operation. The time during which the sdr output is asserted high is the time in which the data on tdi is valid. During that time period, the data is shifted into the tmp_reg shift register. Therefore, tmp_reg gets the data from the Virtual JTAG Intel® FPGA IP core on the tdi output port during a DR scan operation.

There is a 1‑bit register named bypass_reg whose output is connected with tdo logic to maintain the continuity of the scan chain during idle or IR scan shift operation of the Virtual JTAG Intel® FPGA IP core. The tdo logic consists of outputs coming from tmp_reg and bypass_reg and connecting to the tdo input of the Virtual JTAG Intel® FPGA IP core. The tdo logic passes the data from tmp_reg to the Virtual JTAG Intel® FPGA IP core during DR scan shift operations.

The always block of a 4-bit counter also consists of some decode logic. This decode logic uses the load signal and e1dr output signal of the Virtual JTAG Intel® FPGA IP core to load the counter with the contents of tmp_reg. The Virtual JTAG output signal e1dr is asserted high during a DR scan shift operation when all the data is completely shifted into the tmp_reg and sdr has been de-asserted. In addition to sdr and e1dr, there are other outputs from the Virtual JTAG Intel® FPGA IP core that are asserted high to show various states of the TAP controller and internal states of the Virtual JTAG Intel® FPGA IP core. All of these signals can be used to perform different logic operations as needed in your design.

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