Visible to Intel only — GUID: qby1488319314435
Ixiasoft
System Specification
Device Selection
Early System and Board Planning
Pin Connection Considerations for Board Design
I/O and Clock Planning
Design Entry
Design Implementation, Analysis, Optimization, and Verification
Design Checklist
Appendix: Cyclone® 10 GX Transceiver Design Guidelines
Conclusion
Document Revision History
Visible to Intel only — GUID: qby1488319314435
Ixiasoft
Device Selection
This section describes the first step in the Cyclone® 10 GX design process—choosing the device family variant, device density, features, package, and speed grade that best suit your design requirements.
Number | Done? | Checklist Item |
---|---|---|
1 | Select a device based on transceivers, I/O pin count, LVDS channels, package offering, logic/memory/multiplier density, PLLs, clock routing, and speed grade. |