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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Stratix® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Stratix® 10 FPGA IP Design Example User Guide Archives
6. Document Revision History for the HDMI Stratix® 10 FPGA IP Design Example User Guide
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.2. Creating RX-Only or TX-Only Designs
2.3. Hardware and Software Requirements
2.4. Directory Structure
2.5. Design Components
2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
2.7. Design Software Flow
2.8. Running the Design in Different FRL Rates
2.9. Clocking Scheme
2.10. Interface Signals
2.11. Design RTL Parameters
2.12. Hardware Setup
2.13. Simulation Testbench
2.14. Design Limitations
2.15. Debugging Features
3.1. HDMI RX-TX Retransmit Design Block Diagram
3.2. Creating TX or RX Only Designs
3.3. Design Components
3.4. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
3.5. Clocking Scheme
3.6. Interface Signals
3.7. Design RTL Parameters
3.8. Hardware Setup
3.9. Simulation Testbench
3.10. Upgrading Your Design
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3.2. Creating TX or RX Only Designs
For advance users, you can use the HDMI design to create a TX or RX only design.
To use RX or TX only components, remove the irrelevant blocks from the design
User Requirement | Preserve | Remove | Add |
---|---|---|---|
HDMI RX Only | RX Top |
|
— |
HDMI TX Only | TX Top, CPU Sub-System |
|
Video Pattern Generator (custom module or generated from the Video and Image Processing (VIP) Suite) |
Figure 23. Components Required for RX or TX Only Design
Note: If your design only requires HDMI TX or retransmitting HDMI stream from RX to TX through video frame buffer, supply the TX PLL reference clock directly from an external programmable oscillator.