HDMI Stratix® 10 FPGA IP Design Example User Guide

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ID 683701
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Stratix® 10 Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. HDMI 2.0 Design Example 4. HDCP Over HDMI 2.0/2.1 Design Example 5. HDMI Stratix® 10 FPGA IP Design Example User Guide Archives 6. Document Revision History for the HDMI Stratix® 10 FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Stratix® 10 Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Hardware and Software Requirements 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Design Limitation 1.7. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.2. Creating RX-Only or TX-Only Designs 2.3. Hardware and Software Requirements 2.4. Directory Structure 2.5. Design Components 2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.7. Design Software Flow 2.8. Running the Design in Different FRL Rates 2.9. Clocking Scheme 2.10. Interface Signals 2.11. Design RTL Parameters 2.12. Hardware Setup 2.13. Simulation Testbench 2.14. Design Limitations 2.15. Debugging Features
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.15. Debugging Features x
2.15.1. Software Debugging Message 2.15.2. SCDC Information from the Sink Connected to TX 2.15.3. Clock Frequency Measurement
3. HDMI 2.0 Design Example x
3.1. HDMI RX-TX Retransmit Design Block Diagram 3.2. Creating TX or RX Only Designs 3.3. Design Components 3.4. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 3.5. Clocking Scheme 3.6. Interface Signals 3.7. Design RTL Parameters 3.8. Hardware Setup 3.9. Simulation Testbench 3.10. Upgrading Your Design
4. HDCP Over HDMI 2.0/2.1 Design Example x
4.1. High-bandwidth Digital Content Protection (HDCP) 4.2. Nios® V Processor Software Flow 4.3. Design Walkthrough 4.4. Protection of Encryption Key Embedded in FPGA Design 4.5. Security Considerations 4.6. Debug Guidelines
4.1. High-bandwidth Digital Content Protection (HDCP) x
4.1.1. HDCP Over HDMI Design Example Architecture
4.3. Design Walkthrough x
4.3.1. Setting Up the Hardware 4.3.2. Generating the Design 4.3.3. Including HDCP Production Keys 4.3.4. Compiling the Design 4.3.5. Viewing the Results
4.3.3. Including HDCP Production Keys x
4.3.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) 4.3.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
4.3.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) x
4.3.3.1.1. HDCP Key Mapping from DCP Key Files 4.3.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 4.3.3.1.3. hdcp2x_rx_kmem.v file 4.3.3.1.4. hdcp2x_tx_kmem.v file
4.3.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1) x
4.3.3.2.1. Intel KEYENC 4.3.3.2.2. Key Programmer
4.3.5. Viewing the Results x
4.3.5.1. Push Buttons and LED Functions
4.6. Debug Guidelines x
4.6.1. HDCP Status Signals 4.6.2. Modifying HDCP Software Parameters 4.6.3. Frequently Asked Questions (FAQ)
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Stratix® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Stratix® 10 FPGA IP Design Example User Guide Archives
6. Document Revision History for the HDMI Stratix® 10 FPGA IP Design Example User Guide

4.2. Nios® V Processor Software Flow

The Nios® V software flowchart includes the HDCP authentication controls over HDMI application.

Figure 30.  Nios® V Processor Software Flowchart
  1. The Nios® V software initializes and resets the HDMI TX PLL, TX transceiver PHY, I2C master and the external TI retimer.
  2. The Nios® V software polls periodic rate detection valid signal from RX rate detection circuit to determine whether video resolution has changed and if TX reconfiguration is required. The software also polls the TX hot-plug detect signal to determine whether a TX hot-plug event has occurred.
  3. When a valid signal received from RX rate detection circuit, the Nios® V software reads the SCDC and clock depth values from the HDMI RX and retrieves the clock frequency band based on the detected rate to determine whether HDMI TX PLL and transceiver PHY reconfiguration are required. If TX reconfiguration is required, the Nios® V software commands the I2C master to send the SCDC value over to external RX. It then commands to reconfigure the HDMI TX PLL and TX transceiver PHY, followed by device recalibration, and reset sequence. If the rate does not change, neither TX reconfiguration nor HDCP re-authentication is required.
  4. When a TX hot-plug event has occurred, the Nios® V software commands the I2C master to send the SCDC value over to external RX, and then read EDID from RX and update the internal EDID RAM. The software then propagates the EDID information to the upstream.
  5. The Nios® V software starts the HDCP activity by commanding the I2C master to read offset 0x50 from external RX to detect if the downstream is HDCP-capable, or otherwise:
    • If the returned HDCP2Version value is 1, the downstream is HDCP2x-capable.
    • If the returned value of the entire 0x50 reads are 0’s, the downstream is HDCP1x-capable.
    • If the returned value of the entire 0x50 reads are 1’s, the downstream is either not HDCP-capable or inactive.
    • If the downstream is previously not HDCP-capable or inactive but is currently HDCP-capable, the software sets the REPEATER bit of the repeater upstream (RX) to 1 to indicate the RX is now a repeater.
    • If the downstream is previously HDCP-capable but is currently not HDCP-capable or inactive, the software sets the REPEATER bit of to 0 to indicate the RX is now an endpoint receiver.
  6. The software initiates the HDCP2x authentication protocol that includes RX certificate signature verification, master key exchange, locality check, session key exchange, pairing, authentication with repeaters such as topology information propagation.
  7. When in authenticated state, the Nios® V software commands the I2C master to poll the RxStatus register from external RX, and if the software detects the REAUTH_REQ bit is set, it initiates re-authentication and disables TX encryption.
  8. When the downstream is a repeater and the READY bit of the RxStatus register is set to 1, this usually indicates the downstream topology has changed. So, the Nios® V software commands the I2C master to read the ReceiverID_List from downstream and verify the list. If the list is valid and no topology error is detected, the software proceeds to the Content Stream Management module. Otherwise, it initiates re-authentication and disables TX encryption.
  9. The Nios® V software prepares the ReceiverID_List and RxInfo values and then writes to the Avalon® Memory-Mapped Interface Repeater Message port of the repeater upstream (RX). The RX then propagates the list to external TX (upstream).
  10. Authentication is complete at this point. The software enables TX encryption.
  11. The software initiates the HDCP1x authentication protocol that includes key exchange and authentication with repeaters.
  12. The Nios® V software performs link integrity check by reading and comparing Ri’ and Ri from external RX (downstream) and HDCP1x TX respectively. If the values do not match, this indicates loss of synchronization and the software initiates re-authentication and disables TX encryption.
  13. If the downstream is a repeater and the READY bit of the Bcaps register is set to 1, this usually indicates that the downstream topology has changed. So, the Nios® V software commands the I2C master to read the KSV list value from downstream and verify the list. If the list is valid and no topology error is detected, the software prepares the KSV list and Bstatus value and writes to the Avalon® Memory-Mapped Interface Repeater Message port of the repeater upstream (RX). The RX then propagates the list to external TX (upstream). Otherwise, it initiates re-authentication and disables TX encryption.
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