Visible to Intel only — GUID: nkk1523025856722
Ixiasoft
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Stratix® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Stratix® 10 FPGA IP Design Example User Guide Archives
6. Document Revision History for the HDMI Stratix® 10 FPGA IP Design Example User Guide
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.2. Creating RX-Only or TX-Only Designs
2.3. Hardware and Software Requirements
2.4. Directory Structure
2.5. Design Components
2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
2.7. Design Software Flow
2.8. Running the Design in Different FRL Rates
2.9. Clocking Scheme
2.10. Interface Signals
2.11. Design RTL Parameters
2.12. Hardware Setup
2.13. Simulation Testbench
2.14. Design Limitations
2.15. Debugging Features
3.1. HDMI RX-TX Retransmit Design Block Diagram
3.2. Creating TX or RX Only Designs
3.3. Design Components
3.4. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
3.5. Clocking Scheme
3.6. Interface Signals
3.7. Design RTL Parameters
3.8. Hardware Setup
3.9. Simulation Testbench
3.10. Upgrading Your Design
Visible to Intel only — GUID: nkk1523025856722
Ixiasoft
1.5. Compiling and Testing the Design
- Ensure hardware example design generation is complete.
- Launch the Quartus® Prime Pro Edition software and open the .qpf file.
- HDMI 2.1 design example with Support FRL enabled: project directory/quartus/s10_hdmi21_frl_demo.qpf
- HDMI 2.0 design example with Support FRL disabled: project directory/quartus/s10_hdmi2_demo.qpf
- Click Processing > Start Compilation.
- After successful compilation, a .sof file will be generated in your specified directory.
- If you are running HDMI 2.1 design example, you must program the Si5341 programmable oscillator OUT4 to 100 MHz through the Stratix® 10 Clock Control GUI. Otherwise, skip this step.
Figure 5. Si5341 Tab
- Connect to the on-board FMC (J13):
- HDMI 2.1 design example with Support FRL enabled: Bitec HDMI FMC 2.1 Daughter Card (Revision 9)
- HDMI 2.0 design example with Support FRL disabled: Bitec HDMI FMC 2.0 Daughter Card (Revision 11)
- Connect TX (P1) of the Bitec HDMI FMC Daughter Card to an external video source.
- Connect RX (P2) of the Bitec HDMI FMC Daughter Card to an external video sink or video analyzer.
- Ensure all switches on the development board are in default position.
- Configure the selected Stratix® 10 device on the development board using the generated .sof file (Tools > Programmer ).
- The analyzer should display the video generated from the source.
Related Information