HDMI Stratix® 10 FPGA IP Design Example User Guide

ID 683701
Date 4/09/2024
Public
Document Table of Contents

1.5. Compiling and Testing the Design

To compile and run a demonstration test on the hardware example design, follow these steps:
  1. Ensure hardware example design generation is complete.
  2. Launch the Quartus® Prime Pro Edition software and open the .qpf file.
    • HDMI 2.1 design example with Support FRL enabled: project directory/quartus/s10_hdmi21_frl_demo.qpf
    • HDMI 2.0 design example with Support FRL disabled: project directory/quartus/s10_hdmi2_demo.qpf
  3. Click Processing > Start Compilation.
  4. After successful compilation, a .sof file will be generated in your specified directory.
  5. If you are running HDMI 2.1 design example, you must program the Si5341 programmable oscillator OUT4 to 100 MHz through the Stratix® 10 Clock Control GUI. Otherwise, skip this step.
    Figure 5. Si5341 Tab
  6. Connect to the on-board FMC (J13):
    • HDMI 2.1 design example with Support FRL enabled: Bitec HDMI FMC 2.1 Daughter Card (Revision 9)
    • HDMI 2.0 design example with Support FRL disabled: Bitec HDMI FMC 2.0 Daughter Card (Revision 11)
  7. Connect TX (P1) of the Bitec HDMI FMC Daughter Card to an external video source.
  8. Connect RX (P2) of the Bitec HDMI FMC Daughter Card to an external video sink or video analyzer.
  9. Ensure all switches on the development board are in default position.
  10. Configure the selected Stratix® 10 device on the development board using the generated .sof file (Tools > Programmer ).
  11. The analyzer should display the video generated from the source.