Parallel Flash Loader Intel® FPGA IP User Guide

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ID 683698
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Parallel Flash Loader Intel® FPGA IP User Guide
1. Parallel Flash Loader Intel® FPGA IP User Guide x
1.1. Features 1.2. Device Support 1.3. Functional Description 1.4. Using the PFL IP Core 1.5. PFL IP Core In Embedded Systems 1.6. Third-party Programmer Support 1.7. Parameters 1.8. Signals 1.9. Specifications 1.10. Parallel Flash Loader Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide
1.2. Device Support x
1.2.1. Supported Flash Memory Devices 1.2.2. Supported Schemes and Features
1.3. Functional Description x
1.3.1. Programming Flash Memory 1.3.2. Controlling Intel® FPGA Configuration from Flash Memory 1.3.3. Mapping PFL and Flash Address 1.3.4. Implementing Page in the Flash .pof 1.3.5. Using Enhanced Bitstream Compression and Decompression 1.3.6. Using Remote System Upgrade
1.3.1. Programming Flash Memory x
1.3.1.1. Programming CFI Flash 1.3.1.2. Programming Quad SPI Flash 1.3.1.3. Programming NAND Flash
1.3.4. Implementing Page in the Flash .pof x
1.3.4.1. Storing Option Bits
1.3.6. Using Remote System Upgrade x
1.3.6.1. Remote System Upgrade State Machine in the PFL IP Core 1.3.6.2. Implementing Remote System Upgrade with the PFL IP Core 1.3.6.3. User Watchdog Timer
1.4. Using the PFL IP Core x
1.4.1. Converting .sof Files to a .pof 1.4.2. Constraining PFL Timing 1.4.3. Simulating PFL Design 1.4.4. Programming Intel® CPLDs and Flash Memory Devices 1.4.5. Defining New CFI Flash Device 1.4.6. Programming Multiple Flash Memory Devices 1.4.7. Creating Jam Files for Intel® CPLDs and Flash Memory Device Programming
1.4.2. Constraining PFL Timing x
1.4.2.1. Constraining Clock Signal 1.4.2.2. Constraining Synchronous Input and Output Ports 1.4.2.3. Constraining Asynchronous Input and Output Ports, and Bidirectional Synchronous Ports 1.4.2.4. Summary of PFL Timing Constraints
1.4.3. Simulating PFL Design x
1.4.3.1. Creating a Test Bench File for PFL Simulation 1.4.3.2. Performing PFL Simulation in the ModelSim- Intel® FPGA Software 1.4.3.3. Performing PFL Simulation for FPGA Configuration
1.4.4. Programming Intel® CPLDs and Flash Memory Devices x
1.4.4.1. Programming Intel® CPLDs and Flash Memory Devices Separately
1.9. Specifications x
1.9.1. Configuration Time Calculation Examples
1. Parallel Flash Loader Intel® FPGA IP User Guide

1.8. Signals

This section contains information about the PFL IP core input and output signals.
Table 18.  PFL SignalsFor maximum FPGA configuration DCLK frequencies, refer to the Configuration Handbook.
Pin Input or Output Weak Pull-Up Function
pfl_nreset Input — Asynchronous reset for the PFL IP core. Pull high to enable FPGA configuration. To prevent FPGA configuration, pull low when you do not use the PFL IP core. This pin does not affect the flash programming functionality of the PFL IP core.
pfl_flash_access_granted Input — Used for system-level synchronization. This pin is driven by a processor or any arbitrator that controls access to the flash. This active-high pin is connected permanently high if you want the PFL IP core to function as the flash master. Pulling the pfl_flash_access_granted pin low prevents the JTAG interface from accessing the flash and FPGA configuration.
pfl_clk Input — User input clock for the device. Frequency must match the frequency specified in the IP core and must not be higher than the maximum DCLK frequency specified for the specific FPGA during configuration. This pins are not available for the flash programming option in the PFL IP core.
fpga_pgm[] Input — Determines the page for the configuration. This pins are not available for the flash programming option in the PFL IP core.
fpga_conf_done Input 10-kW Pull-Up Resistor Connects to the CONF_DONE pin of the FPGA. The FPGA releases the pin high if the configuration is successful. During FPGA configuration, this pin remains low. This pins are not available for the flash programming option in the PFL IP core.
fpga_nstatus Input 10-kW Pull-Up Resistor Connects to the nSTATUS pin of the FPGA. This pin must be released high before the FPGA configuration and must stay high throughout FPGA configuration. If a configuration error occurs, the FPGA pulls this pin low and the PFL IP core stops reading the data from the flash memory device. This pins are not available for the flash programming option in the PFL IP core.
pfl_nreconfigure Input — After pfl_nreset asserted high for at least fifteen clock cycles, the subsequent low signal at this pin initiates the FPGA reconfiguration. For more flexibility in controlling the FPGA reconfiguration, you can reconnect this pin to a switch to set this input pin high or low. When FPGA reconfiguration is initiated, the fpga_nconfig pin is pulled low to reset the FPGA device. The pfl_clk pin registers this signal. This pins are not available for the flash programming option in the PFL IP core.
pfl_flash_access_request Output — Used for system-level synchronization. When necessary, this pin connects to a processor or an arbitrator. The PFL IP core drives this pin high when the JTAG interface accesses the flash or the PFL IP core configures the FPGA. This output pin works in conjunction with the flash_noe and flash_nwe pins.
flash_addr[] Output — Address inputs for memory addresses. The width of the address bus line depends on the density of the flash memory device and the width of the flash_data bus. The output of this pin depends on the setting of the unused pins if you did not select the PFL interface tri-state option when the PFL is not accessing the flash memory device.
flash_data[] Bidirectional — Data bus to transmit or receive 8- or 16-bit data to or from the flash memory in parallel. The output of this pin depends on the setting of the unused pins if you did not select the PFL interface tri-state option when the PFL is not accessing the flash memory device. 15
flash_nce[] Output — Connects to the nCE pin of the flash memory device. A low signal enables the flash memory device. Use this pin for multiple flash memory device support. The flash_nce pin is connected to each nCE pin of all the connected flash memory devices. The width of this port depends on the number of flash memory devices in the chain.
flash_nwe Output — Connects to the nWE pin of the flash memory device. A low signal enables write operation to the flash memory device.
flash_noe Output — Connects to the nOE pin of the flash memory device. A low signal enables the outputs of the flash memory device during a read operation.
flash_clk Output — Used for burst mode. Connects to the CLK input pin of the flash memory device. The active edges of CLK increment the flash memory device internal address counter. The flash_clk frequency is half of the pfl_clk frequency in burst mode for single CFI flash. In dual P30 or P33 CFI flash solution, the flash_clk frequency runs at a quarter of the pfl_clk frequency. Use this pin for burst mode only. Do not connect these pins from the flash memory device to the CPLD device if you are not using burst mode.
flash_nadv Output — Used for burst mode. Connects to the address valid input pin of the flash memory device. Use this signal for latching the start address. Use this pin for burst mode only. Do not connect these pins from the flash memory device to the CPLD device if you are not using burst mode.
flash_nreset Output — Connects to the reset pin of the flash memory device. A low signal resets the flash memory device.
fpga_data[] Output — Data output from the flash to the FPGA device during configuration. For PS mode, this is a 1-bit bus fpga_data[0] data line. For FPP mode, this is an 8-bit fpga_data[7..0] data bus. This pins are not available for the flash programming option in the PFL IP core.
fpga_dclk Output — Connects to the DCLK pin of the FPGA. Clock input data to the FPGA device during configuration. This pins are not available for the flash programming option in the PFL IP core.
fpga_nconfig Open Drain Output 10-kW Pull-Up Resistor Connects to the nCONFIG pin of the FPGA. A low pulse resets the FPGA and initiates configuration. This pins are not available for the flash programming option in the PFL IP core. 15
flash_sck[] Output — Clock source for flash data read operation. Connects to the CLK input pin of the quad SPI flash. If you use more than one quad SPI flash, connect this pin to the CLK input of all the quad SPI flashes. The width of the port is equivalent to the number of quad SPI flash in the chain. The flash_sck output clock frequency is half of the pfl_clk frequency. When data is read from flash to FPGA, the data is clocked in by the internal flash_sck clock and the clock frequency is equal to pfl_clk frequency.
flash_ncs[] Output — Connects to the ncs pin of the quad SPI flash. If you use more than one quad SPI flash, connect this pin to the ncs pin of all the quad SPI flashes. The width of this port is equivalent to the number of quad SPI flashes in the chain.
flash_io0[] Bidirectional — The first bit of the data bus to or from the quad SPI flash. If you use more than one quad SPI flash, connect this pin to the first bit of the data bus of all the quad SPI flashes. The width of this port is equivalent to the number of quad SPI flashes in the chain.
flash_io1[] Bidirectional — The second bit of the data bus to or from the quad SPI flash. If you use more than one quad SPI flash, connect this pin to the second bit of the data bus of all the quad SPI flashes. The width of this port is equivalent to the number of quad SPI flashes in the chain.
flash_io2[] Bidirectional — The third bit of the data bus to or from the quad SPI flash. If you use more than one quad SPI flash, connect this pin to the third bit of the data bus of all the quad SPI flashes. The width of this port is equivalent to the number of quad SPI flashes in the chain.
flash_io3[] Bidirectional — The fourth bit of the data bus to or from the quad SPI flash. If you use more than one quad SPI flash, connect this pin to the fourth bit of the data bus of all the quad SPI flashes. The width of this port is equivalent to the number of quad SPI flashes in the chain.
pfl_reset_watchdog Input — A toggle signal to reset the watchdog timer before the watchdog timer times out. Hold the signal high or low for at least two clock cycles of the pfl_clk frequency to correctly reset the watchdog timer.
pfl_watchdog_error Output — A high signal indicates an error to the watchdog timer.
15 Intel recommends not inserting logic between the PFL pins and the CPLD I/O pins, especially on the flash_data and fpga_nconfig pins.
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