Parallel Flash Loader Intel® FPGA IP User Guide

Download PDF
ID 683698
Date 4/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. Parallel Flash Loader Intel® FPGA IP User Guide
1. Parallel Flash Loader Intel® FPGA IP User Guide x
1.1. Features 1.2. Device Support 1.3. Functional Description 1.4. Using the PFL IP Core 1.5. PFL IP Core In Embedded Systems 1.6. Third-party Programmer Support 1.7. Parameters 1.8. Signals 1.9. Specifications 1.10. Parallel Flash Loader Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide
1.2. Device Support x
1.2.1. Supported Flash Memory Devices 1.2.2. Supported Schemes and Features
1.3. Functional Description x
1.3.1. Programming Flash Memory 1.3.2. Controlling Intel® FPGA Configuration from Flash Memory 1.3.3. Mapping PFL and Flash Address 1.3.4. Implementing Page in the Flash .pof 1.3.5. Using Enhanced Bitstream Compression and Decompression 1.3.6. Using Remote System Upgrade
1.3.1. Programming Flash Memory x
1.3.1.1. Programming CFI Flash 1.3.1.2. Programming Quad SPI Flash 1.3.1.3. Programming NAND Flash
1.3.4. Implementing Page in the Flash .pof x
1.3.4.1. Storing Option Bits
1.3.6. Using Remote System Upgrade x
1.3.6.1. Remote System Upgrade State Machine in the PFL IP Core 1.3.6.2. Implementing Remote System Upgrade with the PFL IP Core 1.3.6.3. User Watchdog Timer
1.4. Using the PFL IP Core x
1.4.1. Converting .sof Files to a .pof 1.4.2. Constraining PFL Timing 1.4.3. Simulating PFL Design 1.4.4. Programming Intel® CPLDs and Flash Memory Devices 1.4.5. Defining New CFI Flash Device 1.4.6. Programming Multiple Flash Memory Devices 1.4.7. Creating Jam Files for Intel® CPLDs and Flash Memory Device Programming
1.4.2. Constraining PFL Timing x
1.4.2.1. Constraining Clock Signal 1.4.2.2. Constraining Synchronous Input and Output Ports 1.4.2.3. Constraining Asynchronous Input and Output Ports, and Bidirectional Synchronous Ports 1.4.2.4. Summary of PFL Timing Constraints
1.4.3. Simulating PFL Design x
1.4.3.1. Creating a Test Bench File for PFL Simulation 1.4.3.2. Performing PFL Simulation in the ModelSim- Intel® FPGA Software 1.4.3.3. Performing PFL Simulation for FPGA Configuration
1.4.4. Programming Intel® CPLDs and Flash Memory Devices x
1.4.4.1. Programming Intel® CPLDs and Flash Memory Devices Separately
1.9. Specifications x
1.9.1. Configuration Time Calculation Examples
1. Parallel Flash Loader Intel® FPGA IP User Guide

1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.04.03 23.1 19.1.0
  • Added flash_clk and flash_sck information in the Constraining Clock Signal topic..
  • Added description for flash_sck[] in the PFL Signals table.
  • Updated FPP and PS Mode Equations for the PFL table to include additional information for 32 bits flash data width.
2021.07.23 21.1 19.1.0 Corrected the note in Simulating PFL Design to clarify that you can perform PFL simulation using gate-level simulation, which is based on functional netlist.
2021.06.04 21.1 19.1.0 Corrected the constraint type for flash_data in Table: PFL Timing Constraints.
2021.03.29 21.1 19.1.0
  • Added a note about Quad SPI flash in the Converting .sof Files to .pof section.
  • Added Constraining pfl_clk signal in the Timing Analyzer and Constraining fpga_dclk signal in the Timing Analyzer in the Constraining Clock Signal section.
  • Updated Constraining Asynchronous Input and Output Ports to add Bidirectional Synchronous Ports and added Table: Max Delay Calculation.
  • Updated the Constraint Type and Delay Value in the Table: PFL Timing Constraints.
2021.01.19 18.1 18.0
  • Renamed the document title to Parallel Flash Loader Intel® FPGA IP User Guide.
  • Corrected the number of quad SPI flashes supported by the PFL IP core from four to eight in the Programming Quad SPI Flash section.
  • Added Figure: Parallel Flash Loader Intel® FPGA IP Parameter Editor.
  • Updated Figure: Programming Quad SPI Flash Memory Devices With the CPLD JTAG Interface.
  • Updated for latest Intel branding standards.
Document Version Intel® Quartus® Prime Version Changes
2020.03.31 18.1
  • Updated Table: CFI Flash Memory Devices Supported by PFL Intel® FPGA IP Core to add notes about discontinued flash memory devices from Cypress, Macronix, and ESMT.
2019.02.19 18.1
  • Beginning from the Intel® Quartus® Prime software version 18.1, the name of this IP core has been changed from Intel FPGA Parallel Flash Loader IP core to Parallel Flash Loader Intel® FPGA IP core.
  • Added the MT25QU02GCBB device support to the Quad SPI Flash Memory Device Supported by PFL IP Core table.
  • Added a note about the user flash-defined information in the Defining New CFI Flash Device section.
2018.08.06 17.1 Updated the calculation for the Total Clock Cycles and Total Configuration Time at 100 MHz in the Example 3. Page Mode of the Configuration Time Calculation Examples section.
2018.07.10 17.1 Updated the density for the Micron (MT29) device in the NAND Flash Memory Device Supported by PFL IP Core table.
Date Version Changes
November 2017 2017.11.06
  • Updated the Use advance read mode parameter to include latency count options for Intel Burst mode in PFL FPGA Configuration Parameters table.
  • Changed instances of Spansion to Cypress and added note stating Cypress was formerly known as Spansion.
  • Updated values for FIFO size parameter in PFL Flash Programming Parameters.
  • Added link to JEDEC CFI standard in related links.
  • Updated clock cycles to fifteen before pulsing input pin to low in Remote System Upgrade State Machine in the PFL IP Core.
  • Updated description for pfl_nreconfigure signal in PFL Signals table.
  • Rebranded to Intel® .
  • Added Micron MT28EW CFI flash product family support.
  • Added note to all discontinued supported Micron CFI flash memory.
  • Updated flash_io0[], flash_io1[], flash_io2[] and flash_io3[] from output to bidirectional in PFL Signals table.
  • Changed instances of EON Silicon Solution to ESMT and added note stating ESMT was formerly known as EON Silicon Solution.
  • Updated Largest flash density parameter description.
October 2016 2016.10.31
  • Updated Micron flash in CFI Flash Memory Devices Supported by PFL IP Core.
  • Removed FS Spansion flash in Quad SPI Flash Memory Device Supported by PFL IP Core.
  • Updated parameter value in PFL Flash Interface Setting Parameters.
June 2016 2016.06.01
  • Corrected DCLK ratio and Ccfg in Normal Mode and Page Mode examples.
  • Added N25Q256 in Quad SPI Flash Memory Device Supported by PFL IP Core.
  • Removed S25FS512S in Quad SPI Flash Memory Device Supported by PFL IP Core.
  • Edited Parameters table by breaking grouped tables.
  • Updated Number of flash devices used and Largest flash density options in PFL Flash Interface Setting Parameters table
May 2016 2016.05.02
  • Changed instances of Quartus II to Quartus Prime.
  • Added steps to set up PFL simulation using NativeLink and perform ModelSim simulation.
  • Corrected constraint type for fpga_data and fpga_dclk.
  • Corrected DCLK ratio in Normal Mode and Page Mode examples.
  • Corrected Caccess formula for Page Mode configuration time calculation.
  • Corrected delay value for flash_data.
June 2015 2015.06.15 Added support for Spansion S25FS256S and S25FS512S.
January 2015 2015.01.23
  • Corrected DATA width in PFL IP core With Dual P30 or P33 CFI Flash Memory Devices figure.
  • Corrected Spansion part number for S29JL032H and S29JL032H from 229JL032H and 229JL032H respectively.
  • Added Micron MT28GU512AAA1EGC-0SIT and MT28GU01GAAA1EGC-0SIT
  • Added example of programming PFL using command line.
  • Rearranged the supported flash memory device by grouping device families.
  • Added third-party programmer support.
June 2014 2014.06.30 Replaced MegaWizard Plug-In Manager information with IP Catalog.
May 2014 3.2 Updated Table 16 on page 41 to remove Stratix V limitation for the Enhanced bitstream decompression IP core option.
May 2013 3.1 Updated Table 2 on page 5 to add 28F00BP30 and 28F00BP33.
September 2012 3.0
  • Updated manufacturer name from Numonyx to Micron.
  • Updated “Implementing Remote System Upgrade with the PFL IP Core” on page 22, and “Specifications” on page 49
  • Updated Table 4 on page 7, Table 10 on page 30, Table 16 on page 41, Table 17 on page 45, and Table 18 on page 50.
  • Removed figures.
August 2012 2.1 Updated Table 1.
December 2011 2.0
  • Updated “Using Enhanced Bitstream Compression and Decompression” to include reference.
  • Updated Table 1 to include Eon Silicon CFI device EN29GL128 and to remove S29GL-N devices.
  • Updated Table 2 to include Micron QSPI device N25Q128.
  • Updated “Specifications”
  • Updated Table 13 to include FPP x16 and FPP x32 configuration scheme for Stratix V devices.
  • Updated Figure 27.
  • Added Figure 31.
  • Minor text edits
February 2011 1.1
  • Restructured the user guide.
  • Added information about the new feature for the Quartus II software 10.1 release: Support for NAND flash.
July 2010 1.0 Converted from AN386: Using the Parallel Flash Loader With the Quartus II Software.
Level Two Title