Parallel Flash Loader Intel® FPGA IP User Guide

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ID 683698
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Parallel Flash Loader Intel® FPGA IP User Guide
1. Parallel Flash Loader Intel® FPGA IP User Guide x
1.1. Features 1.2. Device Support 1.3. Functional Description 1.4. Using the PFL IP Core 1.5. PFL IP Core In Embedded Systems 1.6. Third-party Programmer Support 1.7. Parameters 1.8. Signals 1.9. Specifications 1.10. Parallel Flash Loader Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide
1.2. Device Support x
1.2.1. Supported Flash Memory Devices 1.2.2. Supported Schemes and Features
1.3. Functional Description x
1.3.1. Programming Flash Memory 1.3.2. Controlling Intel® FPGA Configuration from Flash Memory 1.3.3. Mapping PFL and Flash Address 1.3.4. Implementing Page in the Flash .pof 1.3.5. Using Enhanced Bitstream Compression and Decompression 1.3.6. Using Remote System Upgrade
1.3.1. Programming Flash Memory x
1.3.1.1. Programming CFI Flash 1.3.1.2. Programming Quad SPI Flash 1.3.1.3. Programming NAND Flash
1.3.4. Implementing Page in the Flash .pof x
1.3.4.1. Storing Option Bits
1.3.6. Using Remote System Upgrade x
1.3.6.1. Remote System Upgrade State Machine in the PFL IP Core 1.3.6.2. Implementing Remote System Upgrade with the PFL IP Core 1.3.6.3. User Watchdog Timer
1.4. Using the PFL IP Core x
1.4.1. Converting .sof Files to a .pof 1.4.2. Constraining PFL Timing 1.4.3. Simulating PFL Design 1.4.4. Programming Intel® CPLDs and Flash Memory Devices 1.4.5. Defining New CFI Flash Device 1.4.6. Programming Multiple Flash Memory Devices 1.4.7. Creating Jam Files for Intel® CPLDs and Flash Memory Device Programming
1.4.2. Constraining PFL Timing x
1.4.2.1. Constraining Clock Signal 1.4.2.2. Constraining Synchronous Input and Output Ports 1.4.2.3. Constraining Asynchronous Input and Output Ports, and Bidirectional Synchronous Ports 1.4.2.4. Summary of PFL Timing Constraints
1.4.3. Simulating PFL Design x
1.4.3.1. Creating a Test Bench File for PFL Simulation 1.4.3.2. Performing PFL Simulation in the ModelSim- Intel® FPGA Software 1.4.3.3. Performing PFL Simulation for FPGA Configuration
1.4.4. Programming Intel® CPLDs and Flash Memory Devices x
1.4.4.1. Programming Intel® CPLDs and Flash Memory Devices Separately
1.9. Specifications x
1.9.1. Configuration Time Calculation Examples
1. Parallel Flash Loader Intel® FPGA IP User Guide

1.4.2.3. Constraining Asynchronous Input and Output Ports, and Bidirectional Synchronous Ports

You can exclude asynchronous input ports from the timing analysis of the PFL IP core because the signals on these ports are not synchronous to a IP core clock source. The internal structure of the PFL IP core handles the metastability of these asynchronous signals.

As for asynchronous output ports, the signals can be excluded from the timing analysis because the signals have functionally sufficient timing margin, except flash_nce and flash_addr.

For bidirectional synchronous ports, the flash access during write mode can be excluded because of sufficient timing margin, but not during read mode.

To exclude asynchronous input and output ports from the timing analysis, use the set_false_path command to ignore these ports during timing analysis.

The signal delay from PFL asynchronous output ports to flash memory device (flash_nce, flash_addr) and vice versa (flash_data in read mode) are specified by set_max_delay. The delay calculation is:

Max delay value = Distributed timing budget - board delay

Table 7.  Max Delay Calculation
Flash Access Mode Delay Calculation
Normal Mode

Timing budget = [roundup(Taccess_pfl/Tpfl_clk) + 1] * Tpfl_clk - Taccess

Distribute the timing budget for output and input delay:

Output delay (flash_addr, flash_nce) =

Timing budget (major) – board delay from PFL to flash

Input delay (flash_data) = Timing budget (minor) - board delay from flash to PFL

Page Mode

Timing budget = [roundup(Tpage_access_pfl/Tpfl_clk) + 1]* Tpfl_clk- Tpage_access

Distribute the timing budget for output and input delay:

Output delay (flash_addr, flash_nce) = Timing budget (major) - board delay from PFL to flash

Input delay (flash_data) = Timing budget (minor) - board delay from flash to PFL

Note: Evaluate timing using both Taccess and Tpage_access and select the tighter constraint.

Note:
  1. Taccess_pfl is the flash access time. Refer Table PFL FPGA Configuration Parameters. Tpage_access_pfl is set to 30 ns in the PFL IP core.
  2. Taccess and Tpage_access are FLASH ROM time specification during Normal and Page access respectively.
Note: After you specify all timing constraint settings for the clock signal, on the Constraints menu, click Write SDC File to write all the constraints to a specific .sdc. Then, run full compilation for the PFL design again.
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