Parallel Flash Loader Intel® FPGA IP User Guide

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ID 683698
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Parallel Flash Loader Intel® FPGA IP User Guide
1. Parallel Flash Loader Intel® FPGA IP User Guide x
1.1. Features 1.2. Device Support 1.3. Functional Description 1.4. Using the PFL IP Core 1.5. PFL IP Core In Embedded Systems 1.6. Third-party Programmer Support 1.7. Parameters 1.8. Signals 1.9. Specifications 1.10. Parallel Flash Loader Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide
1.2. Device Support x
1.2.1. Supported Flash Memory Devices 1.2.2. Supported Schemes and Features
1.3. Functional Description x
1.3.1. Programming Flash Memory 1.3.2. Controlling Intel® FPGA Configuration from Flash Memory 1.3.3. Mapping PFL and Flash Address 1.3.4. Implementing Page in the Flash .pof 1.3.5. Using Enhanced Bitstream Compression and Decompression 1.3.6. Using Remote System Upgrade
1.3.1. Programming Flash Memory x
1.3.1.1. Programming CFI Flash 1.3.1.2. Programming Quad SPI Flash 1.3.1.3. Programming NAND Flash
1.3.4. Implementing Page in the Flash .pof x
1.3.4.1. Storing Option Bits
1.3.6. Using Remote System Upgrade x
1.3.6.1. Remote System Upgrade State Machine in the PFL IP Core 1.3.6.2. Implementing Remote System Upgrade with the PFL IP Core 1.3.6.3. User Watchdog Timer
1.4. Using the PFL IP Core x
1.4.1. Converting .sof Files to a .pof 1.4.2. Constraining PFL Timing 1.4.3. Simulating PFL Design 1.4.4. Programming Intel® CPLDs and Flash Memory Devices 1.4.5. Defining New CFI Flash Device 1.4.6. Programming Multiple Flash Memory Devices 1.4.7. Creating Jam Files for Intel® CPLDs and Flash Memory Device Programming
1.4.2. Constraining PFL Timing x
1.4.2.1. Constraining Clock Signal 1.4.2.2. Constraining Synchronous Input and Output Ports 1.4.2.3. Constraining Asynchronous Input and Output Ports, and Bidirectional Synchronous Ports 1.4.2.4. Summary of PFL Timing Constraints
1.4.3. Simulating PFL Design x
1.4.3.1. Creating a Test Bench File for PFL Simulation 1.4.3.2. Performing PFL Simulation in the ModelSim- Intel® FPGA Software 1.4.3.3. Performing PFL Simulation for FPGA Configuration
1.4.4. Programming Intel® CPLDs and Flash Memory Devices x
1.4.4.1. Programming Intel® CPLDs and Flash Memory Devices Separately
1.9. Specifications x
1.9.1. Configuration Time Calculation Examples
1. Parallel Flash Loader Intel® FPGA IP User Guide

1.7. Parameters

Table 14.  PFL General Parameters
Options Value Description
Operating mode
  • Flash Programming and FPGA Configuration
  • Flash Programming
  • FPGA Configuration
 Specifies the operating mode of flash programming and FPGA configuration control in one IP core or separate these functions into individual blocks and functionality.
Targeted flash device
  • CFI Parallel Flash
  • Altera Active Serial ×4
  • Quad SPI Flash
  • NAND Flash
 Specifies the flash memory device connected to the PFL IP core.
Tri-state flash bus On or Off Allows the PFL IP core to tri-state all pins interfacing with the flash memory device when the PFL IP core does not require an access to the flash memory.
Table 15.  PFL Flash Interface Setting Parameters
Options Value Description
Number of flash devices used
  • CFI Parallel Flash: 1–16
  • Altera Active Serial ×4: 1, 2, 4, 8
  • Quad SPI Flash: 1, 2, 4, 8
  • NAND Flash: 1
 Specifies the number of flash memory devices connected to the PFL IP core.
Largest flash density
  • CFI Parallel Flash: 8 Mbit–2 Gbit
  • NAND Flash: 512 Mbit
  • 1 Gbit - Micron (MT29)
  • Altera Active Serial x4: EPCQ 256 Mbit

Specifies the density of the flash memory device to be programmed or used for FPGA configuration. If you have more than one flash memory device connected to the PFL IP core, specify the largest flash memory device density.

For dual mode CFI and NAND flash devices, select the density that is equivalent to the sum of the density of two CFI flashes. For example, if you use two 512-Mb CFI flashes, you must select CFI 1 Gbit. (Available only if you select CFI Parallel Flash or NAND Flash.)

Flash interface data width
  • CFI Parallel Flash: 8, 16, or 32 bits
  • NAND Flash: 8 bits or 16 bits

Specifies the flash data width in bits. The flash data width depends on the flash memory device you use. For multiple flash memory device support, the data width must be the same for all connected flash memory devices.

For CFI flash, select the flash data width that is equivalent to the sum of the data width of two CFI flashes. For example, if you are targeting dual P30 or P33 solution, you must select 32 bits because each CFI flash data width is 16 bits. (Available only if you select CFI Parallel Flash or NAND Flash.)

User control flash_nreset pin On or Off

Creates a flash_nreset pin in the PFL IP core to connect to the reset pin of the flash memory device. A low signal resets the flash memory device. In burst mode, this pin is available by default.

When using a GL flash device, connect this pin to the RESET# pin of the flash device. (Available only if you select CFI Parallel Flash.)

Quad SPI flash device manufacturer
  • Macronix
  • Micron
  • Spansion
 Specifies the device manufacturer of the quad SPI flash. (Available only if you select Quad SPI Flash.)
Quad SPI flash device density 8 Mbit–256 Mbit Specifies the density of the quad SPI flash to be programmed or used for FPGA configuration. (Available only if you select Quad SPI Flash.)
Byte address for reserved block area —

Specifies the start address of the reserved block area for bad block management.

NAND flash memory may contain bad blocks that contain one or more invalid bits. The reserve blocks replace any bad blocks that the PFL IP core encounters. Intel recommends that you reserve a minimum of 2% of the total block. (Available only if you select NAND Flash.)

On-die ECC support On or Off

Enables the support for on-die ECC. Certain NAND flash memory devices has on-die ECC. Allows the PFL IP core to use the on-die ECC of the flash memory device.

Turning off this option allows the PFL IP core to generate its own ECC engine. (Available only if you select NAND Flash.)

Table 16.  PFL Flash Programming Parameters
Options Value Description
Flash programming IP optimization Area, Speed Specifies the flash programming IP optimization. If you optimize the PFL IP core for speed, the flash programming time is shorter but the IP core uses more LEs. If you optimize the PFL IP core for area, the IP core uses less LEs, but the flash programming time is longer. (Available only if you select CFI Parallel Flash.)
FIFO size 16, 32 Specifies the FIFO size if you select Speed for flash programming IP optimization. The PFL IP core uses additional LEs to implement FIFO as temporary storage for programming data during flash programming. With a larger FIFO size, programming time is shorter. (Available only if you select CFI Parallel Flash.)
Add Block-CRC verification acceleration support On or Off Adds a block to accelerate verification. (Available only if you select CFI Parallel Flash.)
Table 17.  PFL FPGA Configuration Parameters
Options Value Description
External clock frequency — Specifies the user-supplied clock frequency for the IP core to configure the FPGA. The clock frequency must not exceed two times the maximum clock (DCLK) frequency acceptable by the FPGA for configuration. The PFL IP core can divide the frequency of the input clock maximum by two.
Flash access time —

Specifies the access time of the flash. You can get the maximum access time that a flash memory device requires from the flash datasheet. Intel recommends specifying a flash access time that is the same as or longer than the required time.

For CFI parallel flash, the unit is in ns and for NAND flash, the unit is in us. NAND flash uses page instead of byte, and requires more access time. This option is disabled for quad SPI flash.

Option bits byte address —

Specifies the start address in which the option bits are stored in the flash memory. The start address must reside on an 8-KB boundary.

See related for more information about option bits.

FPGA configuration scheme
  • PS
  • FPP
  • FPP ×16 (for Stratix V devices)
  • FPP ×32(for Stratix V devices)
 Select the FPGA configuration scheme. The default FPP is FPP ×8. If you are using Stratix V devices, two additional FPP mode is available: FPP ×16 and FPP ×32.
Configuration failure response options Halt, Retry same page, or Retry from fixed address Configuration behavior after configuration failure.
  • If you select Halt, the FPGA configuration stops completely after failure.
  • If you select Retry same page, after failure, the PFL IP core reconfigures the FPGA with data from the same page of the failure.
  • If you select Retry from fixed address, the PFL IP core reconfigures the FPGA with data from a fixed address in the next option field after failure.
Byte address to retry from on configuration failure — If you select Retry from fixed address for configuration failure option, this option specifies the flash address for the PFL IP core to read from the reconfiguration for a configuration failure.
Include input to force reconfiguration On or Off Includes an optional reconfiguration input pin (pfl_nreconfigure) to enable a reconfiguration of the FPGA.
Watchdog timer On or Off Enables a watchdog timer for remote system upgrade support. Turning on this option enables the pfl_reset_watchdog input pin and pfl_watchdog_error output pin, and specifies the time period before the watchdog timer times out. This watchdog timer is a time counter which runs at the pfl_clk frequency.
Time period before the watchdog timer times out — Specifies the time out period of the watchdog timer. The default time out period is 100 ms
Ratio between input clock and DCLK output clock 1, 2, 4, or 8 Specifies the ratio between the input clock and DCLK.
  • Ratio 8 means every eight external clocks to pfl_clk generate one fpga_dclk.
  • Ratio 4 means every four external clocks to pfl_clk generate one fpga_dclk.
  • Ratio 2 means every two external clocks to pfl_clk generate one fpga_dclk.
  • Ratio 1 means every one external clock to pfl_clk generate one fpga_dclk.
Use advance read mode
  • Normal Mode
  • Intel Burst Mode with 3 LC (P30 or P33)
  • Intel Burst Mode with 4 LC (P30 or P33)
  • Intel Burst Mode with 5 LC (P30 or P33)
  • Spansion Page Mode (GL)
  • Micron Burst Mode (M58BW)
 An option to improve the overall flash access time for the read process during the FPGA configuration.
  • Normal mode—Applicable for all flash memory
  • Intel Burst Mode with 3/4/5 LC (P30 or P33)—Applicable for Micron P30 and P33 flash memory only. Reduces sequential read access time. The flash sends valid data after 3/4/5 clock cycles.
  • Spansion page mode—Applicable for Cypress GL flash memory only
  • Micron burst mode—Applicable for Micron M58BW flash memory only
For more information about the read-access modes of the flash memory device, refer to the respective flash memory data sheet.
Enhanced bitstream decompression
  • None
  • Area
  • Speed
 Select to enable or disable the enhanced bitstream decompression block.
  • If you select None, the core disables the enhanced bitstream decompression block.
  • If you select Area, the core optimizes the logic resources used by the enhanced bitstream decompression block in the PFL IP core.
  • If you select Speed, the core optimizes the speed of the data decompression. You can only optimize speed if you select FPP as the FPGA configuration scheme.
Related Information
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