Parallel Flash Loader Intel® FPGA IP User Guide

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ID 683698
Date 4/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. Parallel Flash Loader Intel® FPGA IP User Guide
1. Parallel Flash Loader Intel® FPGA IP User Guide x
1.1. Features 1.2. Device Support 1.3. Functional Description 1.4. Using the PFL IP Core 1.5. PFL IP Core In Embedded Systems 1.6. Third-party Programmer Support 1.7. Parameters 1.8. Signals 1.9. Specifications 1.10. Parallel Flash Loader Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide
1.2. Device Support x
1.2.1. Supported Flash Memory Devices 1.2.2. Supported Schemes and Features
1.3. Functional Description x
1.3.1. Programming Flash Memory 1.3.2. Controlling Intel® FPGA Configuration from Flash Memory Creating Separate PFL Functions 1.3.3. Mapping PFL and Flash Address 1.3.4. Implementing Page in the Flash .pof 1.3.5. Using Enhanced Bitstream Compression and Decompression 1.3.6. Using Remote System Upgrade
1.3.1. Programming Flash Memory x
1.3.1.1. Programming CFI Flash 1.3.1.2. Programming Quad SPI Flash 1.3.1.3. Programming NAND Flash
1.3.4. Implementing Page in the Flash .pof x
1.3.4.1. Storing Option Bits
1.3.6. Using Remote System Upgrade x
1.3.6.1. Remote System Upgrade State Machine in the PFL IP Core 1.3.6.2. Implementing Remote System Upgrade with the PFL IP Core 1.3.6.3. User Watchdog Timer
1.4. Using the PFL IP Core x
1.4.1. Converting .sof Files to a .pof 1.4.2. Constraining PFL Timing 1.4.3. Simulating PFL Design 1.4.4. Programming Intel® CPLDs and Flash Memory Devices 1.4.5. Defining New CFI Flash Device 1.4.6. Programming Multiple Flash Memory Devices 1.4.7. Creating Jam Files for Intel® CPLDs and Flash Memory Device Programming
1.4.2. Constraining PFL Timing x
1.4.2.1. Constraining Clock Signal 1.4.2.2. Constraining Synchronous Input and Output Ports 1.4.2.3. Constraining Asynchronous Input and Output Ports, and Bidirectional Synchronous Ports 1.4.2.4. Summary of PFL Timing Constraints
1.4.3. Simulating PFL Design x
1.4.3.1. Creating a Test Bench File for PFL Simulation 1.4.3.2. Performing PFL Simulation in the ModelSim- Intel® FPGA Software 1.4.3.3. Performing PFL Simulation for FPGA Configuration
1.4.4. Programming Intel® CPLDs and Flash Memory Devices x
1.4.4.1. Programming Intel® CPLDs and Flash Memory Devices Separately
1.9. Specifications x
1.9.1. Configuration Time Calculation Examples
1. Parallel Flash Loader Intel® FPGA IP User Guide

1.3.2. Controlling Intel® FPGA Configuration from Flash Memory

You can use the PFL logic in Intel® CPLDs as a configuration controller for FPGA configuration. The PFL logic in the CPLD determines when to start the configuration process, read the data from the flash memory device, and configure the Intel® FPGA in PS or FPP configuration scheme.
Figure 6. FPGA Configuration With Flash Memory DataFigure shows the Intel® CPLD as the configuration controller for the FPGA. The flash memory includes CFI, quad SPI and NAND flash.

You can use the PFL IP core to either program the flash memory devices, configure your FPGA, or both; however, to perform both functions, create separate PFL functions if any of the following conditions apply to your design:

  • You want to use fewer LEs.
  • You modify the flash data infrequently.
  • You have JTAG or In-System Programming (ISP) access to the Intel® CPLD.
  • You want to program the flash memory device with non- Intel® FPGA data. For example, the flash memory device contains initialization storage for an ASSP. You can use the PFL IP core to program the flash memory device with the initialization data and also create your own design source code to implement the read and initialization control with the CPLD logic.

Creating Separate PFL Functions

To create separate PFL functions, follow these steps:

  1. To create a PFL instantiation, select Flash Programming Only mode.
  2. Assign the pins appropriately.
  3. Compile and generate a .pof for the flash memory device. Ensure that you tri-state all unused I/O pins.
  4. To create another PFL instantiation, select Configuration Control Only mode.
  5. Instantiate this configuration controller into your production design.
  6. Whenever you must program the flash memory device, program the CPLD with the flash memory device .pof and update the flash memory device contents.
  7. Reprogram the CPLD with the production design .pof that includes the configuration controller.
Note: All unused pins are set to ground by default. When programming the configuration flash memory device through the CPLD JTAG pins, you must tri-state the FPGA configuration pins common to the CPLD and the configuration flash memory device. You can use the pfl_flash_access_request and pfl_flash_access_granted signals of the PFL block to tri-state the correct FPGA configuration pins.
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