Parallel Flash Loader Intel® FPGA IP User Guide

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ID 683698
Date 4/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. Parallel Flash Loader Intel® FPGA IP User Guide
1. Parallel Flash Loader Intel® FPGA IP User Guide x
1.1. Features 1.2. Device Support 1.3. Functional Description 1.4. Using the PFL IP Core 1.5. PFL IP Core In Embedded Systems 1.6. Third-party Programmer Support 1.7. Parameters 1.8. Signals 1.9. Specifications 1.10. Parallel Flash Loader Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide
1.2. Device Support x
1.2.1. Supported Flash Memory Devices 1.2.2. Supported Schemes and Features
1.3. Functional Description x
1.3.1. Programming Flash Memory 1.3.2. Controlling Intel® FPGA Configuration from Flash Memory 1.3.3. Mapping PFL and Flash Address 1.3.4. Implementing Page in the Flash .pof 1.3.5. Using Enhanced Bitstream Compression and Decompression 1.3.6. Using Remote System Upgrade
1.3.1. Programming Flash Memory x
1.3.1.1. Programming CFI Flash 1.3.1.2. Programming Quad SPI Flash 1.3.1.3. Programming NAND Flash
1.3.4. Implementing Page in the Flash .pof x
1.3.4.1. Storing Option Bits
1.3.6. Using Remote System Upgrade x
1.3.6.1. Remote System Upgrade State Machine in the PFL IP Core 1.3.6.2. Implementing Remote System Upgrade with the PFL IP Core 1.3.6.3. User Watchdog Timer
1.4. Using the PFL IP Core x
1.4.1. Converting .sof Files to a .pof 1.4.2. Constraining PFL Timing 1.4.3. Simulating PFL Design 1.4.4. Programming Intel® CPLDs and Flash Memory Devices 1.4.5. Defining New CFI Flash Device 1.4.6. Programming Multiple Flash Memory Devices 1.4.7. Creating Jam Files for Intel® CPLDs and Flash Memory Device Programming
1.4.2. Constraining PFL Timing x
1.4.2.1. Constraining Clock Signal 1.4.2.2. Constraining Synchronous Input and Output Ports 1.4.2.3. Constraining Asynchronous Input and Output Ports, and Bidirectional Synchronous Ports 1.4.2.4. Summary of PFL Timing Constraints
1.4.3. Simulating PFL Design x
1.4.3.1. Creating a Test Bench File for PFL Simulation 1.4.3.2. Performing PFL Simulation in the ModelSim- Intel® FPGA Software 1.4.3.3. Performing PFL Simulation for FPGA Configuration
1.4.4. Programming Intel® CPLDs and Flash Memory Devices x
1.4.4.1. Programming Intel® CPLDs and Flash Memory Devices Separately
1.9. Specifications x
1.9.1. Configuration Time Calculation Examples
1. Parallel Flash Loader Intel® FPGA IP User Guide

1.4.1. Converting .sof Files to a .pof

To generate a programming file with different compression features, you must convert the .sof files to a .pof.

To convert the .sof files to a .pof, follow these steps:

  1. On the File menu, click Convert Programming Files.
  2. For Programming file type, specify Programmer Object File (.pof) and name the file.
  3. For Configuration device, select the CFI or NAND flash memory device with the correct density. For example, CFI_32Mb is a CFI device with 32-Megabit (Mb) capacity. (CFI selection is also applicable for Quad SPI flash)
    Note: You must select the correct targeted flash device at Parallel Flash Loader IP Parameter Editor. If you are using Quad SPI flash with the PFL IP Core, you must select only the CFI flash memory device as the configuration device in Convert Programming Files. In Configuration device, Quad SPI option such as EPCQ is not applicable. EPCQ offers Active Serial Mode, which is not compatible with the PFL IP core that supports Passive Mode.
  4. To add the configuration data, under Input files to convert, select SOF Data.
  5. Click Add File and browse to the .sof files you want to add.
    You can place more than one .sof in the same page if you intend to configure a chain of FPGAs. The order of the .sof files must follow the order of the devices in the chain.
    If you want to store the data from other .sof files in a different page, click Add SOF page. Add the .sof files to the new page.
  6. Select SOF Data and click Properties to set the page number and name. Under Address mode for selected pages, select Auto to let the Intel® Quartus® Prime software automatically set the start address for that page. Select Block to specify the start and end addresses, or select Start to specify the start address only.
  7. Click OK.
  8. You can also store Hexadecimal (Intel-Format) File (.hex) user data in the flash memory device:
    1. In the Input files to convert sub-window of the Convert Programming Files window, select Add Hex Data.
    2. In the Add Hex Data dialog box, select either absolute or relative addressing mode.
    • If you select absolute addressing mode, the data in the .hex is programmed in the flash memory device at the exact same address location listed in the .hex.
    • If you select relative addressing mode, specify a start address.
    The data in the .hex is programmed into the flash memory device with the specific start address, and the differences between the addresses are kept. If no address is specified, the Intel® Quartus® Prime software selects an address.
    Note: You can also add other non-configuration data to the .pof by selecting the .hex that contains your data when creating the flash memory device .pof.
  9. Click Options to specify the start address to store the option bits. This start address must be identical to the address you specify when creating the PFL IP core. Ensure that the option bits sector does not overlap with the configuration data pages and that the start address resides on an 8-KB boundary.
  10. If you are using a NAND flash memory device, specify the reserved block start address and the start address (including the option bits) within a 128-KB boundary. To specify the address, in the File/Data area column, select NAND flash Reserved Block and click Properties.
  11. To generate programming files with either the typical or enhanced bitstream compression feature, or both, perform one of the following steps:
    • Typical bitstream compression feature
      1. Select .sof under SOF Data.
      2. Click Properties, and then turn on the Compression option.
      3. Click OK.
    • Enhanced bitstream compression feature
      1. In the Options dialog box, turn on the Enable enhanced bitstream-compression when available option.
      2. Click OK.
    • Double compression technique
      • Perform all the steps for the typical bitstream compression and enhanced bitstream compression features listed above.
    Note: For more information about the compression feature in the PFL IP core, refer to “Using Enhanced Bitstream Compression and Decompression”.
  12. To generate programming files with encrypted data, select .sof under SOF Data and click Properties. Turn on the Generate encrypted bitstream check box.
  13. Click OK to create the .pof.
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