Parallel Flash Loader Intel® FPGA IP User Guide

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ID 683698
Date 7/23/2021
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Document Table of Contents
Document Table of Contents x
1. Parallel Flash Loader Intel® FPGA IP User Guide
1. Parallel Flash Loader Intel® FPGA IP User Guide x
1.1. Features 1.2. Device Support 1.3. Functional Description 1.4. Using the PFL IP Core 1.5. PFL IP Core In Embedded Systems 1.6. Third-party Programmer Support 1.7. Parameters 1.8. Signals 1.9. Specifications 1.10. Parallel Flash Loader Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide
1.2. Device Support x
1.2.1. Supported Flash Memory Devices 1.2.2. Supported Schemes and Features
1.3. Functional Description x
1.3.1. Programming Flash Memory 1.3.2. Controlling Intel® FPGA Configuration from Flash Memory 1.3.3. Mapping PFL and Flash Address 1.3.4. Implementing Page in the Flash .pof 1.3.5. Using Enhanced Bitstream Compression and Decompression 1.3.6. Using Remote System Upgrade
1.3.1. Programming Flash Memory x
1.3.1.1. Programming CFI Flash 1.3.1.2. Programming Quad SPI Flash 1.3.1.3. Programming NAND Flash
1.3.4. Implementing Page in the Flash .pof x
1.3.4.1. Storing Option Bits
1.3.6. Using Remote System Upgrade x
1.3.6.1. Remote System Upgrade State Machine in the PFL IP Core 1.3.6.2. Implementing Remote System Upgrade with the PFL IP Core 1.3.6.3. User Watchdog Timer
1.4. Using the PFL IP Core x
1.4.1. Converting .sof Files to a .pof 1.4.2. Constraining PFL Timing 1.4.3. Simulating PFL Design 1.4.4. Programming Intel® CPLDs and Flash Memory Devices 1.4.5. Defining New CFI Flash Device 1.4.6. Programming Multiple Flash Memory Devices 1.4.7. Creating Jam Files for Intel® CPLDs and Flash Memory Device Programming
1.4.2. Constraining PFL Timing x
1.4.2.1. Constraining Clock Signal 1.4.2.2. Constraining Synchronous Input and Output Ports 1.4.2.3. Constraining Asynchronous Input and Output Ports, and Bidirectional Synchronous Ports 1.4.2.4. Summary of PFL Timing Constraints
1.4.3. Simulating PFL Design x
1.4.3.1. Creating a Test Bench File for PFL Simulation 1.4.3.2. Performing PFL Simulation in the ModelSim- Intel® FPGA Software 1.4.3.3. Performing PFL Simulation for FPGA Configuration
1.4.4. Programming Intel® CPLDs and Flash Memory Devices x
1.4.4.1. Programming Intel® CPLDs and Flash Memory Devices Separately
1.9. Specifications x
1.9.1. Configuration Time Calculation Examples
1. Parallel Flash Loader Intel® FPGA IP User Guide

1.9. Specifications

This section provides the equations to estimate the time for reconfiguring the FPGA with the PFL IP core.
The equations in the following table assume the following definitions:
  • Cflash is the number of clock cycles required to read from flash memory.
  • Ccfg is the number of input clock cycles to clock out the data (producing between one and 16 DCLK cycles, depending on the choice of flash data bus width and FPP or PS mode). Only the larger number between Cflash and Ccfg is important because reading from the flash and clocking out the data for configuration are performed in parallel.
  • Fclk is the input clock frequency to the PFL IP core.
  • Taccess is the flash access time.
  • Caccess is the number of clock cycles required before the data from the flash is ready.
  • Tpage_access is the page read time for Cypress flash memory devices and is only applicable for page mode access. Tpage_access is set to 30 ns in the PFL IP core.
  • N is the number of bytes to be clocked out. This value is obtained from the .rbf for the specific FPGA.
Table 19.  FPP and PS Mode Equations for the PFL
Flash Access Mode Configuration Data Option Flash Data Width (bits) DCLK Ratio = 1, 2, 4, or 8 16
FPP Mode PS Mode
Normal Mode/Page Mode Normal 8

Cflash = Caccess

Ccfg = DCLK Ratio

Coverhead = 5*Caccess

Cflash = Caccess

Ccfg = 8*DCLK Ratio

Coverhead = 5*Caccess

16

Cflash = Caccess/2

Ccfg = DCLK Ratio

Coverhead = 3*Caccess

Cflash = Caccess/2

Ccfg = 8*DCLK Ratio

Coverhead = 3*Caccess

Compressed or encrypted or both 8

Cflash = Caccess

Ccfg = 4*DCLK Ratio

Coverhead = 5*Caccess

Cflash = Caccess

Ccfg = 8*DCLK Ratio

Coverhead = 5*Caccess

16

Cflash = Caccess/2

Ccfg = 4*DCLK Ratio

Coverhead = 3*Caccess

Cflash = Caccess/2

Ccfg = 8*DCLK Ratio

Coverhead = 3*Caccess

Burst Mode Normal 4

Cflash = 4

Ccfg = DCLK Ratio

Coverhead = 48

Cflash = 4

Ccfg = 8*DCLK Ratio

Coverhead = 48

8

Cflash = 2

Ccfg = DCLK Ratio

Coverhead = 22*Caccess+8

Cflash = 2

Ccfg = 8*DCLK Ratio

Coverhead = 22*Caccess+8

16

Cflash = 1

Ccfg = DCLK Ratio

Coverhead = 20*Caccess+8

Cflash = 1

Ccfg = 8*DCLK Ratio

Coverhead = 20*Caccess+8

Compressed or encrypted or both 4

Cflash = 4

Ccfg = 4*DCLK Ratio

Coverhead = 48

Cflash = 4

Ccfg = 8*DCLK Ratio

Coverhead = 48

8

Cflash = 2

Ccfg = 4*DCLK Ratio

Coverhead = 22*Caccess+8

Cflash = 2

Ccfg = 8*DCLK Ratio

Coverhead = 22*Caccess+8

16

Cflash = 1

Ccfg = 4*DCLK Ratio

Coverhead = 20*Caccess+8

Cflash = 1

Ccfg = 8*DCLK Ratio

Coverhead = 20*Caccess+8

  • For Normal Mode and Burst Mode:

    Caccess = Taccess*Fclk+1

    Total Clock Cycles (from nRESET asserted high to N bytes of data clocked out)

    = Coverhead + max(Cflash, Ccfg)*N

    Total Configuration Time = Total Clock Cycle/ PFL Input Clock

  • For Page Mode

    Caccess = [(Taccess*Fclk+1) + ((Tpage_access*Fclk+1)*15)]/16

    Total Clock Cycles (from nRESET asserted high to N bytes of data clocked out)

    = Coverhead + max (Cflash, Ccfg)*N

    Total Configuration Time = Total Clock Cycle/ PFL Input Clock

  • For FPP (×8)

    Total Clock Cycles (from nRESET asserted high to N bytes of data clocked out)

    Cflash remains the same

  • For FPP (×16)

    Total Clock Cycles (from nRESET asserted high to N word of data clocked out)

    Cflash = Cflash × 2 (×2 of Cflash from FPP ×8)

  • For FPP (×32)

    Total Clock Cycles (from nRESET asserted high to N double word of data clocked out)

    Cflash = Cflash × 4 (×4 of Cflash from FPP ×8)

16 Ratio between input clock and DCLK output clock. For more information, see related information
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