Parallel Flash Loader Intel® FPGA IP User Guide

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ID 683698
Date 7/23/2021
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Document Table of Contents
Document Table of Contents x
1. Parallel Flash Loader Intel® FPGA IP User Guide
1. Parallel Flash Loader Intel® FPGA IP User Guide x
1.1. Features 1.2. Device Support 1.3. Functional Description 1.4. Using the PFL IP Core 1.5. PFL IP Core In Embedded Systems 1.6. Third-party Programmer Support 1.7. Parameters 1.8. Signals 1.9. Specifications 1.10. Parallel Flash Loader Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide
1.2. Device Support x
1.2.1. Supported Flash Memory Devices 1.2.2. Supported Schemes and Features
1.3. Functional Description x
1.3.1. Programming Flash Memory 1.3.2. Controlling Intel® FPGA Configuration from Flash Memory 1.3.3. Mapping PFL and Flash Address 1.3.4. Implementing Page in the Flash .pof 1.3.5. Using Enhanced Bitstream Compression and Decompression 1.3.6. Using Remote System Upgrade
1.3.1. Programming Flash Memory x
1.3.1.1. Programming CFI Flash 1.3.1.2. Programming Quad SPI Flash 1.3.1.3. Programming NAND Flash
1.3.4. Implementing Page in the Flash .pof x
1.3.4.1. Storing Option Bits
1.3.6. Using Remote System Upgrade x
1.3.6.1. Remote System Upgrade State Machine in the PFL IP Core 1.3.6.2. Implementing Remote System Upgrade with the PFL IP Core 1.3.6.3. User Watchdog Timer
1.4. Using the PFL IP Core x
1.4.1. Converting .sof Files to a .pof 1.4.2. Constraining PFL Timing 1.4.3. Simulating PFL Design 1.4.4. Programming Intel® CPLDs and Flash Memory Devices 1.4.5. Defining New CFI Flash Device 1.4.6. Programming Multiple Flash Memory Devices 1.4.7. Creating Jam Files for Intel® CPLDs and Flash Memory Device Programming
1.4.2. Constraining PFL Timing x
1.4.2.1. Constraining Clock Signal Constraining pfl_clk signal in the Timing Analyzer Constraining fpga_dclk signal in the Timing Analyzer 1.4.2.2. Constraining Synchronous Input and Output Ports 1.4.2.3. Constraining Asynchronous Input and Output Ports, and Bidirectional Synchronous Ports 1.4.2.4. Summary of PFL Timing Constraints
1.4.3. Simulating PFL Design x
1.4.3.1. Creating a Test Bench File for PFL Simulation 1.4.3.2. Performing PFL Simulation in the ModelSim- Intel® FPGA Software 1.4.3.3. Performing PFL Simulation for FPGA Configuration
1.4.4. Programming Intel® CPLDs and Flash Memory Devices x
1.4.4.1. Programming Intel® CPLDs and Flash Memory Devices Separately
1.9. Specifications x
1.9.1. Configuration Time Calculation Examples
1. Parallel Flash Loader Intel® FPGA IP User Guide

1.4.2.1. Constraining Clock Signal

At any given time, one of the following two clock sources clocks the blocks and modules of the PFL IP core:

  • Clock signals from the pfl_clk ports of the PFL during FPGA configuration
  • TCK pins of the JTAG programming interface during flash programming

The clock signal on the TCK pins is internally constrained to the maximum frequency supported by the selected JTAG programming hardware. Constraining the clock signal is not mandatory.

The pfl_clk generates fpga_dclk according to the ratio between input clock and DCLK output clock, a PFL parameter during FPGA configuration

You can constrain pfl_clk to the maximum frequency that the PFL IP core supports. You can use the create_clock command or the Create Clock dialog box to specify the period and duty cycle of the clock constraint.

You can constrain fpga_dclk using create_generated_clock command or the Create Generated Clock dialog box to specify the relationship to source based on the ratio between input clock and DCLK output clock.

Constraining pfl_clk signal in the Timing Analyzer

To constrain the pfl_clk signal in the Timing Analyzer, follow these steps:

  1. Run full compilation for the PFL design. Ensure that the timing analysis tool is set to Timing Analyzer.
  2. After full compilation completes, on the Tools menu, select Timing Analyzer to launch the Timing Analyzer window.
  3. In the Tasks list, under Diagnostic, click Report Unconstrained Paths to view the list of unconstrained parts and ports of the PFL design
  4. In the Report list, under Unconstrained Paths, click Clock Summary to view the clock that requires constraints. The default setting for all unconstrained clocks is 1 GHz. To constrain the clock signal, right-click the clock name and select Edit Clock Constraint.
  5. In the Create Clock dialog box, set the period and the duty cycle of the clock constraint
  6. Click Run

Constraining fpga_dclk signal in the Timing Analyzer

To constrain the fpga_dclk signal in the Timing Analyzer, follow these steps:

  1. Run full compilation for the PFL design. Ensure that the timing analysis tool is set to Timing Analyzer.
  2. After full compilation completes, on the Tools menu, select Timing Analyzer to launch the Timing Analyzer window.
  3. In the Tasks list, click Update Timing Netlist, to include newly added clocks, constraints and exceptions.
  4. On the Constraint menu, select Create Generated Clock to launch the dialog box.
  5. In the Create Generated Clock dialog box, set the relationship to source of the clock constraint.
  6. Click Run
  7. If input clock to DCLK output clock ratio more than 1, open the data window using Set Muticycle Path on the Constraint menu.
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