Parallel Flash Loader Intel® FPGA IP User Guide

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ID 683698
Date 7/23/2021
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Document Table of Contents
Document Table of Contents x
1. Parallel Flash Loader Intel® FPGA IP User Guide
1. Parallel Flash Loader Intel® FPGA IP User Guide x
1.1. Features 1.2. Device Support 1.3. Functional Description 1.4. Using the PFL IP Core 1.5. PFL IP Core In Embedded Systems 1.6. Third-party Programmer Support 1.7. Parameters 1.8. Signals 1.9. Specifications 1.10. Parallel Flash Loader Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Parallel Flash Loader Intel® FPGA IP User Guide
1.2. Device Support x
1.2.1. Supported Flash Memory Devices 1.2.2. Supported Schemes and Features
1.3. Functional Description x
1.3.1. Programming Flash Memory 1.3.2. Controlling Intel® FPGA Configuration from Flash Memory 1.3.3. Mapping PFL and Flash Address 1.3.4. Implementing Page in the Flash .pof 1.3.5. Using Enhanced Bitstream Compression and Decompression 1.3.6. Using Remote System Upgrade
1.3.1. Programming Flash Memory x
1.3.1.1. Programming CFI Flash 1.3.1.2. Programming Quad SPI Flash 1.3.1.3. Programming NAND Flash
1.3.4. Implementing Page in the Flash .pof x
1.3.4.1. Storing Option Bits
1.3.6. Using Remote System Upgrade x
1.3.6.1. Remote System Upgrade State Machine in the PFL IP Core 1.3.6.2. Implementing Remote System Upgrade with the PFL IP Core 1.3.6.3. User Watchdog Timer
1.4. Using the PFL IP Core x
1.4.1. Converting .sof Files to a .pof 1.4.2. Constraining PFL Timing 1.4.3. Simulating PFL Design 1.4.4. Programming Intel® CPLDs and Flash Memory Devices 1.4.5. Defining New CFI Flash Device 1.4.6. Programming Multiple Flash Memory Devices 1.4.7. Creating Jam Files for Intel® CPLDs and Flash Memory Device Programming
1.4.2. Constraining PFL Timing x
1.4.2.1. Constraining Clock Signal 1.4.2.2. Constraining Synchronous Input and Output Ports 1.4.2.3. Constraining Asynchronous Input and Output Ports, and Bidirectional Synchronous Ports 1.4.2.4. Summary of PFL Timing Constraints
1.4.3. Simulating PFL Design x
1.4.3.1. Creating a Test Bench File for PFL Simulation 1.4.3.2. Performing PFL Simulation in the ModelSim- Intel® FPGA Software 1.4.3.3. Performing PFL Simulation for FPGA Configuration
1.4.4. Programming Intel® CPLDs and Flash Memory Devices x
1.4.4.1. Programming Intel® CPLDs and Flash Memory Devices Separately
1.9. Specifications x
1.9.1. Configuration Time Calculation Examples Normal Mode Page Mode Burst Mode Single Quad SPI Flash Four Cascaded Quad SPI Flashes
1. Parallel Flash Loader Intel® FPGA IP User Guide

1.9.1. Configuration Time Calculation Examples

The following are the configuration time calculation examples for normal mode, page mode, and burst mode:

Note: Any reference to the core clock speed of 100 MHz is only an example of the configuration time calculation and not a recommendation of the actual clock.

Normal Mode

  • Normal mode configuration time calculation:

    .rbf size for EP2S15 = 577KB = 590,848 Bytes

    Configuration mode = FPP without data compression or encryption

    Flash access mode = Normal Mode

    Flash data bus width = 16 bits

    Flash access time = 100 ns

    PFL input Clock = 100 MHz

    DCLK ratio = 2

  • Use the following formulas in this calculation:

    Caccess = Taccess*Fclk+1

    Cflash for Normal Mode = Caccess / 2

    Ccfg = 2

    Coverhead = 3*Caccess

    Total Clock Cycles = Coverhead + max (Cflash, Ccfg)*N

    Total Configuration Time = Total Clock Cycle/ PFL Input Clock

  • Substitute these values in the following formulas:

    Caccess = (100ns * 100MHz) + 1 = 11

    Cflash = 11/2 = 5.5

    Ccfg = 2

    Coverhead = 3*11 = 33

    Total Clock Cycles = 33 + 5.5 * 590848 = 3249697

    Total Configuration Time at 100 MHz = 3249697/ 100 × 106 = 32.5ms

Page Mode

  • Page mode configuration time calculation:

    .rbf size for EP2S15 = 577 KB = 590,848 Bytes

    Configuration mode = FPP without data compression or encryption

    Flash access mode = Page Mode

    Flash data bus width = 16 bits

    Flash access time = 100 ns

    PFL input Clock = 100 MHz

    DCLK ratio = 2

  • Use the following formulas in this calculation:

    Tpage_access = 30 ns

    Caccess = [(Taccess*Fclk+1) + ((Tpage_access*Fclk+1)*15)]/16

    Cflash for Page Mode = Caccess / 2

    Ccfg = 2

    Coverhead = 3* Caccess

    Total Clock Cycles = Coverhead + max (Cflash, Ccfg)*N

    Total Configuration Time = Total Clock Cycle/ PFL Input Clock

  • Substitute these values in the following formulas:

    Caccess = [((100ns * 100 MHz) + 1) + (30ns*100 MHz*15)]/16 = 3.5

    Cflash for Page Mode = 3.5/ 2 = 1.75 = 2

    Ccfg = 2

    Coverhead = 3*3.5 = 10.5

    Total Clock Cycles = 10.5 + 2*590848 = 1181706.5

    Total Configuration Time at 100 MHz = 1181706.5 / 100 × 106 = 11.82 ms

Burst Mode

  • Burst mode configuration time calculation:

    .rbf size for EP2S15 = 577KB = 590,848 Bytes

    Configuration mode = FPP without data compression or encryption

    Flash access mode = Burst Mode

    Flash data bus width = 16 bits

    Flash access time = 100 ns

    PFL input Clock = 100 MHz

    DCLK ratio = 2

  • Use the following formulas in this calculation:

    Caccess = Taccess*Fclk+1

    Cflash for Burst Mode = 1

    Ccfg = 2

    Coverhead = 20* Caccess + 8

    Total Clock Cycles = Coverhead + max (Cflash, Ccfg)*N

    Total Configuration Time = Total Clock Cycle/ PFL Input Clock

  • Substitute these values in the following formulas:

    Caccess = (100ns * 100 MHz) + 1 = 11

    Cflash = 1

    Ccfg = 2

    Coverhead = (20*11)+8 = 228

    Total Clock Cycles = 228 + 2 * 590848 = 1181924

    Total Configuration Time at 100 MHz = 1181924 / 100 × 106 = 11.82 ms

Single Quad SPI Flash

  • Single quad SPI flash configuration time calculation

    .rbf size for EP2S15 = 577KB = 590,848 Bytes

    Configuration mode = FPP without data compression or encryption

    Flash access mode = Burst Mode

    Flash data bus width = 4 bits (only one quad SPI flash is used)

    Flash access time = 100 ns

    PFL input Clock = 100 MHz

    DCLK ratio = 2

  • Use the following formulas in this calculation:

    Cflash = 4

    Ccfg = 2

    Coverhead = 48

    Total Clock Cycles = Coverhead + max (Cflash, Ccfg)*N

    Total Configuration Time = Total Clock Cycle/ PFL Input Clock

  • Substitute these values in the following formulas:

    Cflash = 4

    Ccfg = 2

    Coverhead = 48

    Total Clock Cycles = 48 + 4 * 590848 = 2363440

    Total Configuration Time at 100 MHz = 2363440 / 100 × 106 = 23.63 ms

Four Cascaded Quad SPI Flashes

  • Four cascaded quad SPI flashes configuration time calculation:

    .rbf size for EP2S15 = 577KB = 590,848 Bytes

    Configuration mode = FPP without data compression or encryption

    Flash access mode = Burst Mode

    Flash data bus width = 16 bits (total bus width for four quad SPI flashes)

    Flash access time = 100 ns

    PFL input Clock = 100 MHz

    DCLK ratio = 2

The configuration time calculation for four cascaded quad SPI flash is identical to the configuration time calculation for CFI flash with 16 bit flash data width.

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