Visible to Intel only — GUID: fgf1583958202909
Ixiasoft
Visible to Intel only — GUID: fgf1583958202909
Ixiasoft
2.4. Simulating the eCPRI IP
The eCPRI IP supports the Synopsys* VCS* , Synopsys* VCS* MX, Siemens* EDA QuestaSim* , Aldec* Riviera-PRO* and Xcelium* Parallel simulators. The eCPRI IP generates a Verilog HDL and VHDL simulation model. The IP parameter editor offers you the option of generating a Verilog HDL or VHDL simulation model for the IP core. The IP design example also supports Verilog HDL/VHDL simulation model or testbench.
For more information about functional simulation models for Intel FPGA IPs, refer to the Simulating Intel FPGA Designs chapter in Quartus Prime Pro Edition User Guide: Third-party Simulation.