eCPRI Intel® FPGA IP User Guide

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ID 683685
Date 12/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the eCPRI IP 2. Getting Started 3. eCPRI IP Parameters 4. Functional Description 5. Interfaces 6. eCPRI IP Registers 7. eCPRI Intel FPGA IP User Guide Archives 8. Document Revision History for the eCPRI Intel® FPGA IP User Guide
1. About the eCPRI IP x
1.1. eCPRI Intel® FPGA IP Features 1.2. eCPRI IP Device Family Support 1.3. eCPRI Intel® FPGA IP Device Speed Grade Support 1.4. eCPRI IP Resource Utilization 1.5. Intel® FPGA IP Core Verification 1.6. eCPRI IP Release Information
2. Getting Started x
2.1. Installing and Licensing the eCPRI IP 2.2. Specifying the eCPRI IP Parameters 2.3. eCPRI IP Generated File Structure 2.4. Simulating the eCPRI IP 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the eCPRI IP Parameters x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. High Level Data Path Flow 4.2. Operation of the eCPRI IP Blocks
4.1. High Level Data Path Flow x
4.1.1. Transmit TX Path 4.1.2. Receive RX Path 4.1.3. Supported Ethernet Variants
4.2. Operation of the eCPRI IP Blocks x
4.2.1. Packet Classifier 4.2.2. Ethernet Header Insertion/Removal 4.2.3. Concatenation/De-concatenation 4.2.4. Header Mapper/De-Mapper 4.2.5. eCPRI IWF Type 0 4.2.6. eCPRI Message 5 Packet Parser 4.2.7. Packet Queue 4.2.8. eCPRI Message Type 4.2.9. Error Handling 4.2.10. RX Throttling
4.2.8. eCPRI Message Type x
4.2.8.1. eCPRI Message Type 0- IQ Data Transfer 4.2.8.2. eCPRI Message Type 1- Bit Sequence Transfer 4.2.8.3. eCPRI Message Type 2- Real Time Control Data 4.2.8.4. eCPRI Message Type 3- Generic Data Transfer 4.2.8.5. eCPRI Message Type 4- Remote Memory Access 4.2.8.6. eCPRI Message Type 5- One-Way Delay Measurement 4.2.8.7. eCPRI Message Type 6- Remote Reset 4.2.8.8. eCPRI Message Type 7- Event Indication 4.2.8.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interfaces x
5.1. eCPRI IP Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals 5.7.4. F-Tile Ethernet Hard IP 1588 PTP Signals 5.7.5. Agilex 5 Device Ethernet Hard IP 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
1. About the eCPRI IP
2. Getting Started
3. eCPRI IP Parameters
4. Functional Description
5. Interfaces
6. eCPRI IP Registers
7. eCPRI Intel FPGA IP User Guide Archives
8. Document Revision History for the eCPRI Intel® FPGA IP User Guide

5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface

Table 56.  Signals of CPRI 32-bit Ctrl_AxC Interface
Signal Name Width (Bits) I/O Direction Description
TX Interface
rtvs64_tx_ready[N] 1 Input Indicates that CPRI mapper is ready to read a real-time vendor-specific byte from rtvs_tx_data on the next clock cycle.
rtvs64_tx_valid[N] 1 Output Write valid for rtvs_tx_data. Assert this signal to indicate rtvs_tx_data holds a valid value in the current clock cycle
rtvs64_tx_data[N] 64 Output Real-time vendor-specific word to be written to the CPRI frame.

The CPRI mapper writes the current value of the rtvs_tx_data bus to the CPRI frame based on the rtvs_tx_ready signal from the previous cycle, and the rtvs_tx_valid signal in the current cycle.

RX Interface
rtvs64_rx_valid[N] 1 Input Each asserted bit indicates the corresponding byte on the current rtvs_rx_data bus is a valid real-time vendor-specific byte.
rtvs64_rx_data[N] 64 Input Indicates real-time vendor-specific word received from the CPRI frame. The rtvs_rx_valid signal indicates which bytes are valid vendor specific bytes.
Level Two Title