eCPRI Intel® FPGA IP User Guide

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ID 683685
Date 8/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the eCPRI IP 2. Getting Started 3. eCPRI IP Parameters 4. Functional Description 5. Interface Overview 6. eCPRI IP Registers 7. eCPRI Intel FPGA IP User Guide Archives 8. Document Revision History for the eCPRI Intel® FPGA IP User Guide
1. About the eCPRI IP x
1.1. eCPRI Intel® FPGA IP Features 1.2. eCPRI IP Device Family Support 1.3. eCPRI Intel® FPGA IP Device Speed Grade Support 1.4. eCPRI IP Resource Utilization 1.5. Intel® FPGA IP Core Verification 1.6. eCPRI IP Release Information
2. Getting Started x
2.1. Installing and Licensing 2.2. Specifying the IP Core Parameters and Options 2.3. eCPRI IP Generated File Structure 2.4. Simulating the eCPRI IP 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Interfaces 4.2. High Level Data Path Flow 4.3. Operation of the eCPRI IP Blocks
4.2. High Level Data Path Flow x
4.2.1. Transmit TX Path 4.2.2. Receive RX Path 4.2.3. Supported Ethernet Variants
4.3. Operation of the eCPRI IP Blocks x
4.3.1. Packet Classifier 4.3.2. Ethernet Header Insertion/Removal 4.3.3. Concatenation/De-concatenation 4.3.4. Header Mapper/De-Mapper 4.3.5. eCPRI IWF Type 0 4.3.6. eCPRI Message 5 Packet Parser 4.3.7. Packet Queue 4.3.8. eCPRI Message Type 4.3.9. Error Handling 4.3.10. RX Throttling
4.3.8. eCPRI Message Type x
4.3.8.1. eCPRI Message Type 0- IQ Data Transfer 4.3.8.2. eCPRI Message Type 1- Bit Sequence Transfer 4.3.8.3. eCPRI Message Type 2- Real Time Control Data 4.3.8.4. eCPRI Message Type 3- Generic Data Transfer 4.3.8.5. eCPRI Message Type 4- Remote Memory Access 4.3.8.6. eCPRI Message Type 5- One-Way Delay Measurement 4.3.8.7. eCPRI Message Type 6- Remote Reset 4.3.8.8. eCPRI Message Type 7- Event Indication 4.3.8.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interface Overview x
5.1. eCPRI IP Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals 5.7.4. F-Tile Ethernet Hard IP 1588 PTP Signals 5.7.5. Agilex 5 Device Ethernet Hard IP 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
1. About the eCPRI IP
2. Getting Started
3. eCPRI IP Parameters
4. Functional Description
5. Interface Overview
6. eCPRI IP Registers
7. eCPRI Intel FPGA IP User Guide Archives
8. Document Revision History for the eCPRI Intel® FPGA IP User Guide

5.12. eCPRI IP Sink Interface

Table 45.  Signals of the eCPRI IP Sink InterfaceThis table lists the ports from client logic to eCPRI IP. All signals are synchronous to clk_tx.
Signal Name Width Direction Description
avst_sink_valid 1 Input Avalon® sink valid from client logic to eCPRI.

Continuously assert avst_sink_valid between the assertions of avst_sink_sop and avst_sink_eop. The only exception to this rule is when the avst_sink_ready signal deasserts. In this case, deassert avst_sink_valid for three cycles of READY_LATENCY.

avst_sink_data DATA_WIDTH 9 Input Avalon® sink write data from RRH PHY to eCPRI
avst_sink_sop 1 Input Avalon® sink start of packet (SOP) from RRH PHY to eCPRI. Indicate the beginning of packet.
avst_sink_eop 1 Input Avalon® sink end of packet (EOP) from RRH PHY to eCPRI. Indicate the end of packet.
avst_sink_empty LOG2(DATA_WIDTH9/8) Input Avalon® sink empty from RRH PHY to eCPRI. Indicates the number of symbols that are empty, that is, do not represent valid data.
avst_sink_ready 1 Output Avalon® sink ready driven from eCPRI. Indicates eCPRI can accept data.
avst_sink_error 1 Input Avalon® sink error from RRH PHY to eCPRI. A bit mask to mark errors affecting the data being transferred in the current cycle.
Sideband
sink_pkt_size 16 Input Packet size in bytes for the data packet from client logic to eCPRI IP. The packet size must not include data on sideband signal interface.

This port is available only when the Streaming mode is enabled in the eCPRI IP.

Ensure that you send the data packet with the correct size. If the packet size (sink_pkt_size) does not match the packet size of the whole SOP and EOP, the Avalon® streaming interface error to MAC is asserted. This sets eCPRI TX error register as well.

sink_pc_id 32 Input

Physical channel ID of the eCPRI message.

For message type 3, the physical channel is 32-bit wide. For other message types, it is 16-bit wide and the 16 bit MSB is ignored. Valid on SOP assertion and stable until EOP assertion.

sink_seq_id 32 Input

Sequence ID of eCPRI message.

For message type 3, the physical channel is 32-bit wide. For other message types, it is 16-bit wide and the 16 bit MSB is ignored. Valid on SOP assertion and stable until EOP assertion.

sink_rtc_id 16 Input

Real time control ID of eCPRI message.

Valid on SOP assertion and stable until EOP assertion.

sink_concatenation 1 Input
Concatenation indication on the eCPRI message:

  • 0 - Indicates that the eCPRI message is the last one inside the eCPRI PDU.

  • 1 - Indicates that another eCPRI message follows this one within the eCPRI PDU.
Valid on SOP assertion and stable until EOP assertion.
sink_msg_type 8 Input

Indicate message type of the eCPRI message. Valid range is 0-7 and 64-255 for eCPRI v1.2 specification.

Valid on SOP assertion and stable until EOP assertion.

sink_mem_acc_id 8 Input

Indicate remote memory access id of the eCPRI message type 4:

Valid on SOP assertion and stable until EOP assertion.

sink_op_type 8 Input
Indicate operation of the eCPRI message type 4:
  • 8’b0000 0000 – Read Request
  • 8’b0000 0001 – Read Response
  • 8’b0001 0000 – Write Request
  • 8’b0001 0001 – Write Response
  • 8’b0010 xxxx – Write No Response
  • 8’bxxxx 0010 – Failure No Response
Valid on SOP assertion and stable until EOP assertion.
sink_element_id 16 Input

Indicates element id of the eCPRI message type 4.

Valid on SOP assertion and stable until EOP assertion.

sink_address 48 Input

Indicates memory address of the eCPRI message type 4.

Valid on SOP assertion and stable until EOP assertion.

sink_length 16 Input

Indicates memory access length of the eCPRI message type 4.

Valid on SOP assertion and stable until EOP assertion.

sink_reset_id 16 Input

Indicates reset ID of the eCPRI message type 6.

Valid on SOP assertion and stable until EOP assertion.

sink_reset_op 8 Input
Indicates reset operation type of the eCPRI message type 6:
  • 8’b0000 0001 – Remote Reset Request
  • 8’b0000 0010 – Remote Reset Response
  • Others – Reserved
Valid on SOP assertion and stable until EOP assertion.
sink_event_id 8 Input

Indicate event ID of the eCPRI message type 7.

Valid on SOP assertion and stable until EOP assertion.

sink_event_type 8 Input

Indicates event type of the eCPRI message type 7.

Valid on SOP assertion and stable until EOP assertion.

9 This is set to 64. This parameter is hidden from user and you can't change it.
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