eCPRI Intel® FPGA IP User Guide

Download PDF
ID 683685
Date 12/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the eCPRI IP 2. Getting Started 3. eCPRI IP Parameters 4. Functional Description 5. Interfaces 6. eCPRI IP Registers 7. eCPRI Intel FPGA IP User Guide Archives 8. Document Revision History for the eCPRI Intel® FPGA IP User Guide
1. About the eCPRI IP x
1.1. eCPRI Intel® FPGA IP Features 1.2. eCPRI IP Device Family Support 1.3. eCPRI Intel® FPGA IP Device Speed Grade Support 1.4. eCPRI IP Resource Utilization 1.5. Intel® FPGA IP Core Verification 1.6. eCPRI IP Release Information
2. Getting Started x
2.1. Installing and Licensing the eCPRI IP 2.2. Specifying the eCPRI IP Parameters 2.3. eCPRI IP Generated File Structure 2.4. Simulating the eCPRI IP 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the eCPRI IP Parameters x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. High Level Data Path Flow 4.2. Operation of the eCPRI IP Blocks
4.1. High Level Data Path Flow x
4.1.1. Transmit TX Path 4.1.2. Receive RX Path 4.1.3. Supported Ethernet Variants
4.2. Operation of the eCPRI IP Blocks x
4.2.1. Packet Classifier 4.2.2. Ethernet Header Insertion/Removal 4.2.3. Concatenation/De-concatenation 4.2.4. Header Mapper/De-Mapper 4.2.5. eCPRI IWF Type 0 4.2.6. eCPRI Message 5 Packet Parser 4.2.7. Packet Queue 4.2.8. eCPRI Message Type 4.2.9. Error Handling 4.2.10. RX Throttling
4.2.8. eCPRI Message Type x
4.2.8.1. eCPRI Message Type 0- IQ Data Transfer 4.2.8.2. eCPRI Message Type 1- Bit Sequence Transfer 4.2.8.3. eCPRI Message Type 2- Real Time Control Data 4.2.8.4. eCPRI Message Type 3- Generic Data Transfer 4.2.8.5. eCPRI Message Type 4- Remote Memory Access 4.2.8.6. eCPRI Message Type 5- One-Way Delay Measurement 4.2.8.7. eCPRI Message Type 6- Remote Reset 4.2.8.8. eCPRI Message Type 7- Event Indication 4.2.8.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interfaces x
5.1. eCPRI IP Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals 5.7.4. F-Tile Ethernet Hard IP 1588 PTP Signals 5.7.5. Agilex 5 Device Ethernet Hard IP 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
1. About the eCPRI IP
2. Getting Started
3. eCPRI IP Parameters
4. Functional Description
5. Interfaces
6. eCPRI IP Registers
7. eCPRI Intel FPGA IP User Guide Archives
8. Document Revision History for the eCPRI Intel® FPGA IP User Guide

4.2.3. Concatenation/De-concatenation

The Concatenation/De-concatenation blocks of the eCPRI IP implements concatenation logic of the eCPRI messages into single Ethernet frame or single IP/UDP packet. The sink_concatenation sideband signal identifies packets that required concatenation. The below diagrams illustrates the eCPRI messages with and without concatenation.
Figure 7. eCPRI Message Concatenation
When multiple eCPRI messages are concatenated together, 0 to 3 "zero" padding bytes are added if the following message does not start at a 4 byte boundary. The payload size specified in the eCPRI common header does not include this extra zero padding bytes.
Figure 8. Concatenation/De-concatenation Example Waveform
The above waveform shows two incoming eCPRI messages entering to eCPRI IP, first eCPRI message with concatenation sideband interface signal = 1 and the second eCPRI message with concatenation sideband interface signal = 0. These two eCPRI messages are combined and send through single transport network layer protocol. On the receiving end, the combined eCPRI message will then de-concatenate into 2 eCPRI messages and output to Avalon® streaming interface.

There is a timeout counter used to detect the end of the concatenation message. If the counter overflows and no message with C=0 is detected, an error will be logged and the message with C=1 will be converted to message with C=0 and send to MAC.

The message type allowed for concatenation is restricted to message type 0,1,2,3 and 6. The de-concatenation is supported on all message type except message type 5.

There are 2 different eCPRI packet concatenation scenarios which trigger error and it is shown in below diagram.
Figure 9. eCPRI Packet Concatenation Scenario 1
In the first scenario, there are three incoming Avalon® streaming interface packets payload size of 500 bytes, 600 bytes and 700 bytes. The total payload size after concatenation is 1800 bytes which is bigger than maximum eCPRI IP supported maximum transmission unit (MTU) size of 1500 bytes. In this case, error will be logged in the eCPRI TX error message register and payload 0 and 1 will be sent as concatenated packets while payload 2 will be sent by itself.
Figure 10. eCPRI Packet Concatenation Scenario 2
In the second scenario, the first packet payload size is more than 1500 bytes. In this case, all the packets drop and error logged in eCPRI TX error message register.
Level Two Title