Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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ID 683675
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 50G Ethernet IP Core 2. Getting Started 3. Low Latency 50G Ethernet Intel® FPGA IP Parameters 4. Functional Description 5. Interfaces and Signal Descriptions 6. IP Core Register Descriptions 7. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices
1. About the Low Latency 50G Ethernet IP Core x
1.1. Release Information 1.2. Supported Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. IP Core Verification 1.6. Performance and Resource Utilization
1.5. IP Core Verification x
1.5.1. Simulation Environment 1.5.2. Compilation Checking 1.5.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Low Latency 50G Ethernet IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Placement Settings for the Low Latency 50G Ethernet IP Core
4. Functional Description x
4.1. TX MAC Datapath 4.2. TX PCS 4.3. RX MAC Datapath 4.4. RX PCS 4.5. Link Fault Signaling Interface 4.6. User Interface to Ethernet Transmission 4.7. Auto Negotiation and Link Training 4.8. Flow Control 4.9. Reset
4.1. TX MAC Datapath x
4.1.1. Frame Padding 4.1.2. Preamble Insertion 4.1.3. Inter-Packet Gap Generation and Insertion
4.3. RX MAC Datapath x
4.3.1. IP Core Preamble Processing 4.3.2. IP Core Strict SFD Checking 4.3.3. IP Core Malformed Packet Handling 4.3.4. Length/Type Field Processing 4.3.5. RX CRC Checking and Dynamic Forwarding
4.3.4. Length/Type Field Processing x
4.3.4.1. Length Checking
4.6. User Interface to Ethernet Transmission x
4.6.1. Order of Transmission 4.6.2. Bit Order For TX and RX Datapaths
4.8. Flow Control x
4.8.1. TX Pause/PFC Flow Control Transmission 4.8.2. XON/XOFF Pause Frames
5. Interfaces and Signal Descriptions x
5.1. TX MAC Interface to User Logic 5.2. RX MAC Interface to User Logic 5.3. Transceivers 5.4. Transceiver Reconfiguration Signals 5.5. Avalon® Memory-Mapped Management Interface 5.6. Miscellaneous Status and Debug Signals 5.7. Reset Signals 5.8. Flow Control Interface
5.4. Transceiver Reconfiguration Signals x
5.4.1. Disabling Background Calibration
6. IP Core Register Descriptions x
6.1. PHY Registers 6.2. TX MAC Registers 6.3. RX MAC Registers 6.4. Flow Control Registers 6.5. Statistics Registers 6.6. Auto-Negotiation and Link Training Registers
6.5. Statistics Registers x
6.5.1. TX Statistics Registers 6.5.2. RX Statistics Registers
6.6. Auto-Negotiation and Link Training Registers x
6.6.1. AN/LT Sequencer Config 6.6.2. AN/LT Sequencer Status 6.6.3. Auto Negotiation Config Register 1 6.6.4. Auto Negotiation Config Register 2 6.6.5. Auto Negotiation Status Register 6.6.6. Auto Negotiation Config Register 3 6.6.7. Auto Negotiation Config Register 4 6.6.8. Auto Negotiation Config Register 5 6.6.9. Auto Negotiation Config Register 6 6.6.10. Auto Negotiation Status Register 1 6.6.11. Auto Negotiation Status Register 2 6.6.12. Auto Negotiation Status Register 3 6.6.13. Auto Negotiation Status Register 4 6.6.14. Auto Negotiation Status Register 5 6.6.15. Link Training Config Register 1 6.6.16. Link Training Config Register 2 6.6.17. Link Training Status Register 1 6.6.18. Link Training Config Register for Lane 0 6.6.19. Link Training Frame Contents for Lane 0 6.6.20. Local Transceiver TX EQ 1 Settings for Lane 0 6.6.21. Local Transceiver TX EQ 2 Settings for Lane 0 6.6.22. Local Link Training Parameters 6.6.23. Link Training Config Register for Lane 1 6.6.24. Link Training Frame Contents for Lane 1 6.6.25. Local Transceiver TX EQ 1 Settings for Lane 1 6.6.26. Local Transceiver TX EQ 2 Settings for Lane 1 6.6.27. Link Training Config Register for Lane 2 6.6.28. Link Training Frame Contents for Lane 2 6.6.29. Local Transceiver TX EQ 1 Settings for Lane 2 6.6.30. Local Transceiver TX EQ 2 Settings for Lane 2 6.6.31. Link Training Config Register for Lane 3 6.6.32. Link Training Frame Contents for Lane 3 Link Training Frame Contents for Lane 3 Fields 6.6.33. Local Transceiver TX EQ 1 Settings for Lane 3 6.6.34. Local Transceiver TX EQ 2 Settings for Lane 3
1. About the Low Latency 50G Ethernet IP Core
2. Getting Started
3. Low Latency 50G Ethernet Intel® FPGA IP Parameters
4. Functional Description
5. Interfaces and Signal Descriptions
6. IP Core Register Descriptions
7. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

6.6.32. Link Training Frame Contents for Lane 3

Provides CSRs for the following fields that are transmitted during link training to the link partner for Lane 3
  • TX EQ Coefficient Request to Link Partner on Lane 3
  • INIT Coefficients command to Link Partner on Lane 3
  • PRESET Coefficients command to Link Partner on Lane 3
  • Local TX EQ Coefficient Status for Lane 3
  • Local Receiver Ready Status for Lane 3
  • Most Recent TX EQ Coefficient Request from Link Partner on Lane 3
  • Most Recent INIT command from Link Partner on Lane 3
  • Most Recent PRESET command from Link Partner on Lane 3
  • Most Recent TX EQ Status from Link Partner on Lane 3
  • Most Recent Receiver Ready Status from Link Partner on Lane 3

Offset: 0xE9

Access: RO and RW

Link Training Frame Contents for Lane 3 Fields

Bit Name Description Access Reset
30 lp_receiver_ready_ln3 Link Partner Receiver Ready Status for Lane 3

1: The link partner receiver has determined that training is complete and is prepared to receive data

0: The link partner receiver is requesting that training continue

RO 0x0
29:24 lp_coefficient_status_ln3 TX EQ Coefficient Status from Link Partner for Lane 3

[5:4] Status of Link Partner (+1) TX EQ Coefficient

[3:2] Status of Link Partner (0) TX EQ Coefficient

[1:0] Status of Link Partner (-1) TX EQ Coefficient

The Coefficient values are encoded as follows:
  • 2'b00: Hold
  • 2'b01: Increment
  • 2'b10: Decrement
  • 2'b11: Reserved
 RO 0x0
23 lp_preset_coefficients_ln3 PRESET Command from Link Partner on Lane 3

1: Set local TX EQ to PRESET

0: Normal Operation

This Field is normally Read-only, and the values are normally controlled by the Remote Partner Link Training SM.

When ovride_local_coef_enable=1, this field becomes writable, and is used to set the local values.

When ovride_local_coef_enable=1, use updated_local_coef_ln3=1 to write the local values.

RW 0x0
22 lp_initialize_coefficients_ln3 INIT Command from Link Partner on Lane 3

1: Set local TX EQ to INIT

0: Normal Operation

This Field is normally Read-only, and the values are normally controlled by the Remote Partner Link Training SM.

When ovride_local_coef_enable=1, this field becomes writable, and is used to set the local values.

When ovride_local_coef_enable=1, use updated_local_coef_ln3=1 to write the local values.

RW 0x0
21:16 lp_coefficient_update_ln3 TX EQ Coefficient Request from Link Partner on Lane 3

[5:4] Control for Local (+1) TX EQ Coefficient

[3:2] Control for Local (0) TX EQ Coefficient

[1:0] Control for Local (-1) TX EQ Coefficient

This Field is normally Read-only, and the values are normally controlled by the Remote Partner Link Training SM.

When ovride_local_coef_enable=1, this Field becomes writable, and is used to set the local values.

When ovride_local_coef_enable=1, use updated_local_coef_ln3=1 to write the local values.

The Coefficient values are encoded as follows:
  • 2'b00: Hold
  • 2'b01: Increment
  • 2'b10: Decrement
  • 2'b11: Reserved
 RW 0x0
14 ld_receiver_ready_ln3 Local Receiver Ready Status for Lane 3

1: The local device receiver has determined that training is complete and is prepared to receive data

0: The local device receiver is requesting that training continue

RO 0x0
13:8 ld_coefficient_status_ln3 Local TX EQ Coefficient Status for Lane 3

[5:4] Status of Local (+1) TX EQ Coefficient

[3:2] Status of Local (0) TX EQ Coefficient

[1:0] Status of Local (-1) TX EQ Coefficient

The Coefficient values are encoded as follows:
  • 2'b00: Hold
  • 2'b01: Increment
  • 2'b10: Decrement
  • 2'b11: Reserved
 RO 0x0
7 ld_preset_coefficients_ln3 PRESET Coefficients command to Link Partner on Lane 3

1: PRESET Coefficients

0: Normal Operation

This field is normally Read-only, and the values are normally controlled by the Link Training SM.

When ovride_lp_coef_enable=1, this field becomes writable, and is used to set the values sent to the Link Partner.

When ovride_lp_coef_enable=1, useupdated_lp_coef_ln3=1 to transmit the values to the Link Partner.

The PRESET command is defined in IEEE 802.3 CL72.6.10.2.3.1.

RW 0x0
6 ld_initialize_coefficients_ln3 INIT Coefficients command to Link Partner on Lane 3

1: INIT Coefficients

0: Normal Operation

This field is normally Read-only, and the values are normally controlled by the Link Training SM.

When ovride_lp_coef_enable=1, this field becomes writable, and is used to set the values sent to the Link Partner.

When ovride_lp_coef_enable=1, useupdated_lp_coef_ln3=1 to transmit the values to the Link Partner.

The INIT command is defined in IEEE 802.3 CL72.6.10.2.3.2.

RW 0x0
5:0 ld_coefficient_update_ln3 TX EQ Coefficient Request to Link Partner on Lane 3

[5:4] Control for Link Partner (+1) TX EQ Coefficient

[3:2] Control for Link Partner (0) TX EQ Coefficient

[1:0] Control for Link Partner (-1) TX EQ Coefficient

This field is normally Read-only, and the values are normally controlled by the Link Training SM.

When ovride_lp_coef_enable=1, this field becomes writable, and is used to set the values sent to the Link Partner.

When ovride_lp_coef_enable=1, use updated_lp_coef_ln3=1 to transmit the values to the Link Partner.

The Coefficient values are encoded as follows:
  • 2'b00: Hold
  • 2'b01: Increment
  • 2'b10: Decrement
  • 2'b11: Reserved
 RW 0x0
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