Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

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ID 683675
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 50G Ethernet IP Core 2. Getting Started 3. Low Latency 50G Ethernet Intel® FPGA IP Parameters 4. Functional Description 5. Interfaces and Signal Descriptions 6. IP Core Register Descriptions 7. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices
1. About the Low Latency 50G Ethernet IP Core x
1.1. Release Information 1.2. Supported Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. IP Core Verification 1.6. Performance and Resource Utilization
1.5. IP Core Verification x
1.5.1. Simulation Environment 1.5.2. Compilation Checking 1.5.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Low Latency 50G Ethernet IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Placement Settings for the Low Latency 50G Ethernet IP Core
4. Functional Description x
4.1. TX MAC Datapath 4.2. TX PCS 4.3. RX MAC Datapath 4.4. RX PCS 4.5. Link Fault Signaling Interface 4.6. User Interface to Ethernet Transmission 4.7. Auto Negotiation and Link Training 4.8. Flow Control 4.9. Reset
4.1. TX MAC Datapath x
4.1.1. Frame Padding 4.1.2. Preamble Insertion 4.1.3. Inter-Packet Gap Generation and Insertion
4.3. RX MAC Datapath x
4.3.1. IP Core Preamble Processing 4.3.2. IP Core Strict SFD Checking 4.3.3. IP Core Malformed Packet Handling 4.3.4. Length/Type Field Processing 4.3.5. RX CRC Checking and Dynamic Forwarding
4.3.4. Length/Type Field Processing x
4.3.4.1. Length Checking
4.6. User Interface to Ethernet Transmission x
4.6.1. Order of Transmission 4.6.2. Bit Order For TX and RX Datapaths
4.8. Flow Control x
4.8.1. TX Pause/PFC Flow Control Transmission 4.8.2. XON/XOFF Pause Frames
5. Interfaces and Signal Descriptions x
5.1. TX MAC Interface to User Logic 5.2. RX MAC Interface to User Logic 5.3. Transceivers 5.4. Transceiver Reconfiguration Signals 5.5. Avalon® Memory-Mapped Management Interface 5.6. Miscellaneous Status and Debug Signals 5.7. Reset Signals 5.8. Flow Control Interface
5.4. Transceiver Reconfiguration Signals x
5.4.1. Disabling Background Calibration
6. IP Core Register Descriptions x
6.1. PHY Registers 6.2. TX MAC Registers 6.3. RX MAC Registers 6.4. Flow Control Registers 6.5. Statistics Registers 6.6. Auto-Negotiation and Link Training Registers
6.5. Statistics Registers x
6.5.1. TX Statistics Registers 6.5.2. RX Statistics Registers
6.6. Auto-Negotiation and Link Training Registers x
6.6.1. AN/LT Sequencer Config 6.6.2. AN/LT Sequencer Status AN/LT Sequencer Status Fields 6.6.3. Auto Negotiation Config Register 1 6.6.4. Auto Negotiation Config Register 2 6.6.5. Auto Negotiation Status Register 6.6.6. Auto Negotiation Config Register 3 6.6.7. Auto Negotiation Config Register 4 6.6.8. Auto Negotiation Config Register 5 6.6.9. Auto Negotiation Config Register 6 6.6.10. Auto Negotiation Status Register 1 6.6.11. Auto Negotiation Status Register 2 6.6.12. Auto Negotiation Status Register 3 6.6.13. Auto Negotiation Status Register 4 6.6.14. Auto Negotiation Status Register 5 6.6.15. Link Training Config Register 1 6.6.16. Link Training Config Register 2 6.6.17. Link Training Status Register 1 6.6.18. Link Training Config Register for Lane 0 6.6.19. Link Training Frame Contents for Lane 0 6.6.20. Local Transceiver TX EQ 1 Settings for Lane 0 6.6.21. Local Transceiver TX EQ 2 Settings for Lane 0 6.6.22. Local Link Training Parameters 6.6.23. Link Training Config Register for Lane 1 6.6.24. Link Training Frame Contents for Lane 1 6.6.25. Local Transceiver TX EQ 1 Settings for Lane 1 6.6.26. Local Transceiver TX EQ 2 Settings for Lane 1 6.6.27. Link Training Config Register for Lane 2 6.6.28. Link Training Frame Contents for Lane 2 6.6.29. Local Transceiver TX EQ 1 Settings for Lane 2 6.6.30. Local Transceiver TX EQ 2 Settings for Lane 2 6.6.31. Link Training Config Register for Lane 3 6.6.32. Link Training Frame Contents for Lane 3 6.6.33. Local Transceiver TX EQ 1 Settings for Lane 3 6.6.34. Local Transceiver TX EQ 2 Settings for Lane 3
1. About the Low Latency 50G Ethernet IP Core
2. Getting Started
3. Low Latency 50G Ethernet Intel® FPGA IP Parameters
4. Functional Description
5. Interfaces and Signal Descriptions
6. IP Core Register Descriptions
7. Document Revision History for the Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

6.6.2. AN/LT Sequencer Status

Provides the following status bits:
  • Link Ready
  • AN Timeout
  • LT Timeout
  • Sequencer mode for PCS reconfiguration

Offset: 0xB1

Access: RO

AN/LT Sequencer Status Fields

Bit Name Description Access Reset
13:8 seq_reconfig_mode Sequencer mode for PCS reconfiguration

6'b000001: AN mode

6'b000010: LT mode (Clause 93)

6'b100000: 50G data mode

All other settings are reserved

  • The sequencer modifies the datapath as required to move through the stages of AN/LT
  • This status register lets you know which step is in progress, and how the datapath is configured
RO 0x0
2 seq_lt_timeout Sequencer Link Training Timeout

1: Sequencer had LT Timeout

0: No timeout occurred

This status bit is sticky, and stays high until the next time LT restarts 		RO 0x0
1 seq_an_timeout Sequencer Auto Negotiation Timeout

1: Sequencer had AN Timeout

0: No timeout occurred

This status bit is sticky, and stays high until the next time AN restarts 		RO 0x0
0 seq_link_ready Sequencer Link Ready

1: The AN/LT Sequencer thinks the link is ready for data mode

0: Link not ready

  • This bit is determined by the RX PCS lane alignment status and hi_ber indication, depending on the setting of 0xB0[13] Link Fail if HiBER
  • If 0xB0[2] Disable Link Fail Timer is set, then the sequencer continues to indicate Link Ready and stay in data mode even if the link status goes down
RO 0x0
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