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1. Agilex™ 7 Configuration User Guide
2. Agilex™ 7 Configuration Details
3. Agilex™ 7 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Agilex™ 7 Configuration Features
7. Agilex™ 7 Debugging Guide
8. Agilex™ 7 Configuration User Guide Archives
9. Document Revision History for the Agilex™ 7 Configuration User Guide
2.1. Agilex™ 7 Configuration Timing Diagram
2.2. Configuration Flow Diagram
2.3. Device Response to Configuration and Reset Events
2.4. Additional Clock Requirements for HPS and Transceivers
2.5. Agilex™ 7 Configuration Pins
2.6. Configuration Clocks
2.7. Agilex™ 7 Configuration Time Estimation
2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II)
3.1.7.1. Functional Description
3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration
3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP
3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP
3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP
3.1.7.6. Supported Flash Memory Devices
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II Intel® FPGA IP
3.1.7.3.2. Mapping Parallel Flash Loader II Intel® FPGA IP and Flash Address
3.1.7.3.3. Creating a Single Parallel Flash Loader II Intel® FPGA IP for Programming and Configuration
3.1.7.3.4. Creating Separate Parallel Flash Loader II Intel® FPGA IP Functions
3.1.7.4.1. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for using CFI Flash
3.1.7.4.4. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Input Pins
3.1.7.4.5. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Skew Tolerance Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.7. Debugging Guidelines for RSU Configuration
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Agilex™ 7 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. E-Tile Transceivers May Fail To Configure
7.8. Understanding and Troubleshooting Configuration Pin Behavior
7.9. Configuration Debugger Tool
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5.5.2. Generating an Application Image
You can generate the RSU image from the command line directly, by running the quartus_pfg with the following arguments:
quartus_pfg -c fpga.sof application.rpd -o mode=ASX4 -o bitswap=ON
Alternatively, you can use the Quartus® Prime Pro Edition Programming File Generator to generate the .rpd image by completing the following procedure:
- On the File menu, click Programming File Generator.
- Select Agilex™ 7 from the Device family drop-down list.
- Select the configuration mode from the Configuration mode drop-down list. The current Quartus® Prime only supports remote system update feature in Active Serial x4.
- On the Output Files tab, assign the output directory and file name.
- Select the output file type.
- Raw Programming File (.rpd)
- By default, the .rpd file type is little-endian, if you are using a third-party programmer that does not support the little-endian format. Set the Bit swap to On to generate the .rpd file in big endian format.
Note: The rsu1.tcl script that Intel provides performs the bit swap operation. Consequently, if you are using this script, set Bit swap to Off.
- On the Input Files tab, click Add Bitstream. Change the Files of type to SRAM Object File (*.sof). Then, select application image .sof file and click Open.
Figure 77. Specify the .sof File
- Click Generate to generate the remote system update programming files. You can now program the flash memory. You can save the configuration in a .pfg file for later use.