• Added information for steps related to Agilex™ 7 devices supporting multiple QSPI flash memory devices in the Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image section.
• Updated the nINIT_DONE signal in the Power-On, Configuration, and Reconfiguration Timing Diagram and the Using nINIT_DONE to Gate the PLL_Reset Signal diagrams.
• Updated the Agilex™ 7 Configuration Time Estimation section.
• Added additional information resource for HPS Boot First in the Additional Clock Requirements for HPS and Transceivers section.
• Updated the descriptions for the following commands in the Command List and Description table in the Operation Commands section.
  • QSPI_ERASE
  • CONFIG_STATUS

• Clarified dependencies for EMIF, MIPI, and PHY Lite interfaces in the OSC_CLK_1 Clock Input section.
• Updated the last step in the Programming Serial Flash Devices using the JTAG Interface section.
• Added paragraph regarding the nINIT_DONE signal behavior during configuration in the Gating the PLL Reset Signal section.

• Updated the AVST_READY signal in the Power-On, Configuration, and Reconfiguration Timing Diagram.
• Removed the link up requirement value and added note about delay before configuration in the AS Fast Mode of the Agilex™ 7 Configuration Overview section.
• Removed CvP periphery image configuration time in the Agilex™ 7 Configuration Time Estimation section.
• Removed the PCIe power-up-to-active time value in the Debugging Guidelines for the AS Configuration Scheme section.
• Updated note in the CONF_DONE and INIT_DONE section.

• Added AGF 006, AGF 008, AGI 035, AGI 040, and AGI 041 and to the Configuration Time for Various Configuration Modes table in the Agilex™ 7 Configuration Time Estimation section.

• Replaced Bitstream with RBF in column heading, and added AGM 032 and AGM 039 to the Configuration Time for Various Configuration Modes table in the Agilex™ 7 Configuration Time Estimation section.
• Added note regarding VID devices in the CONF_DONE and INIT_DONE section.
• Updated the notes in Step 4 in the Enabling Dual-Purpose Pins section to clarify dependencies for designs with HPS.
• Clarified dependencies for EMIF, MIPI, and PHY Lite interfaces in the OSC_CLK_1 Clock Input section.
• Replaced 133 MHz with 166 MHz in the AS_CLK section.
• Added new section Configuration Debugger Tool.

• Updated the description for the QSPI_OPEN and QSPI_SET_CS commands in the Command List and Description table in section Operation Commands.
• Updated the error code recovery for value C in the Error Code Recovery for Known Error Codes table in the Error Code Recovery section.
• Updated the CONF_DONE and INIT_DONE signals in the Power-On, Configuration, and Reconfiguration Timing Diagram, Recoverable Error during Reconfiguration Timing Diagram, and the Unrecoverable Error during Reconfiguration Timing Diagram.
• Added note after the Power-On, Configuration, and Reconfiguration Timing Diagram about the CONF_DONE and INIT_DONE signals.

• Added table Configuration Firmware Pointer Block Contents to the Adding an Application Image section.
• Added figure Verify the Writes to the Removing an Application Image section.
• Removed footnote and MX66U2G45G54 from the Quad SPI Flash Memory Devices Supported by PFL II Intel FPGA IP Core table.
• Replaced 0x02000000 with 0x03FF0000 as the new image pointer entry in the Adding an Application Image and Removing an Application Image sections.

• Updated Figure Remove Application Image.

• Updated the following sections to reflect latest supported memories:
  • PFL II Parameters
  • Mapping PFL II IP Core and Flash Address
  • Supported Flash Memory Devices
• Updated the following sections with information regarding enabling direct factory image fallback.
  • Generating the Initial RSU Image Using RBF Files
  • Generating a Factory Update Image
• Updated the following sections with importance of factory image input file selection to generate the initial RSU image.
  • Generating the Initial RSU Image Using SOF Files
  • Generating the Initial RSU Image Using RBF Files
• Added new section Debugging Guidelines for RSU Configuration.
• Updated product family name to " Intel Agilex® 7".
• Retitled the document from Intel® Agilex™ Configuration User Guide to Intel Agilex® 7 Configuration User Guide.

• Updated the SDM I/O Pins for Power Management and SmartVID section to include new figure Specifying the PMBus mode pins and information to control the VID regulator.
• Updated the Configuration Time for Various Configuration Modes table.
• Replaced mentions of Agilex SX with Agilex devices that support HPS.
• Updated Using Multiple Serial Flash Devices, Command Sequence to Perform Quad SPI Operation, and Operation Commands to add information for accessing multiple serial flash devices with Mailbox Client IP in AS mode.
• Updated the Available SDM I/O Pin Assignments for Configuration Signals that Do Not Use Dedicated SDM I/O Pins table to match Quartus® Prime.
• Corrected the factory and application image addresses in the Reconfiguring the Device with an Application or Factory Image section.
• Added Maximum Allowable External nCSO Pin Skew Delay Guidelines section.

• Added bootrom recovery feature information to the Intel® Agilex™ Configuration Timing Diagram section.
• Added dual-purpose pins restrictions to the Enabling Dual-Purpose Pins section.
• Updated the Configuration Time for Various Configuration Modes table.

• Updated the Specifying the Page Command Setting diagram and added reference to the Power Management and VID implementation guide in the SDM I/O Pins for Power Management and SmartVID section.
• Removed the note stating Intel® Agilex™ device configuration is not available in the IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core - Functional Description section.
• Updated the Maximum Allowable External AS_DATA Pin Skew Delay Guidelines section.
• Removed the step on Hyperflex® registers initialization in the Device Initialization section.
• Removed the Preventing Register Initialization During Power-On section.
• Added a note on read-only flag in the Sub-Partition Table Layout section.
• Updated pin status description for the CONFIG_STATUS command in the Command List and Description table.
• Removed topic: Application Image Layout
• Removed references to the Application Image Layout topic in the following sections:
  • RSU Image Layout in Flash – SDM Perspective
  • Sub-Partition Table Layout
  • Modifying the List of Application Images
• Added a note on absolute address option removal in the Generating Remote System Update Image Files Using the Programming File Generator section.
• Removed content relevant to absolute address option from the following sections:
  • Generating an Application Image
  • Generating a Factory Update Image
• Removed the note stating to contact sales representative for more information about the device security support in Intel® Agilex™ production devices from the Device Security section.

• Updated footnote text in the Intel® Agilex™ Configuration Scheme, Data Width, and MSEL table.
• Updated REFCLK_GXR clock guidelines in the Additional Clock Requirements for HPS and Transceivers.
• Added link to the Pin Connection Guidelines in Device Configuration Pins for Optional Configuration Signals.
• Updated list of recommended voltage regulators in SDM I/O Pins for Power Management and SmartVID.
• Added HPS-based serial flash memory layout diagrams in Serial Flash Memory Layout.
• Revised list of the supported third-party flash devices in Understanding Quad SPI Flash Byte-Addressing.
• Minor edits and updates in Chapter 5: Remote System Update (RSU) to improve the clarity:
  • Revised Configuration pointer block, Initial RSU image, and factory update image descriptions in the RSU Glossary table.
  • Added a note in Remote System Update Configuration Sequence.
  • Revised RSU_STATUS information in RSU Recovery from Corrupted Images.
  • Revised steps description in Update with the Factory Update Image and Guidelines for Performing Remote System Update Functions for Non-HPS.
  • Revised pointer block description in RSU Image Layout in Flash – SDM Perspective.
  • Revised reliable operation statement in RSU Image Layout – Your Perspective.
  • Added a note in RSU Image Sub-Partitions Layout.
  • Revised the 0x14 offset description in Configuration Pointer Block Layout.
  • Aligned steps across the Generating the Initial RSU Image sub-sections.
  • Aligned steps across the Generating the Application Image sub-sections.

• Removed the Configuration Pins I/O Standard, Drive Strength, and IBIS Model section.
  • Replaced content with a section listing the I/O standards and features for configuration pins in different configuration schemes.
  • Added IBIS Model.
• Revised the Power-On, Configuration, and Reconfiguration Timing Diagram figure.
• Added text about I/O pins in SDM and HPS banks in Configuration Flow Diagram.
• Added note about valid nSTATUS response in Intel® Agilex™ Configuration Timing Diagram and The AVST_READY Signal sections.

• Added R-tile transceiver clock requirement in Additional Clock Requirements for HPS and Transceivers
• Updated MSEL in the MSEL Pull-Up and Pull-Down Circuit Diagram figure.
• Updated SDM I/O Pins for Power Management and SmartVID:
  • Replaced ISL82XX with LTC3888 device
  • Added Page Command setting description
• Corrected the maximum size of the first bitstream section value in OSC_CLK_1 Requirements. The maximum size is 512 KB.
• Added new topic: Generating Compressed SOF File
• Renamed the Compact Flash Memory to the External Non-Volatile Flash Memory in the following figures:
  • Connections for Avalon® -ST x8 Single-Device Configuration
  • Connections for Avalon® -ST x16 Single-Device Configuration
  • Connections for Avalon® -ST x32 Single-Device Configuration
• Globally added R_UP registers description in the AS and JTAG-related figures.
• Updated IP for Use with the Avalon-ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core. Added note about PFL II IP maximum throughput.
• Added guidance about JTAG configuration failure in the Debugging Guidelines for the JTAG Configuration Scheme.
• Removed CONF_DONE configuration function from the Required Configuration Signals for the AS Configuration Scheme table.
• Added .rpd programming file in the Output File Types table in the AS Configuration Scheme Hardware Components and File Types.
• Revised JTAG Configuration
• Removed QSF Assignment for AS topic.
• Added video describing reset importance in the Including the Reset Release Intel® FPGA IP in Your Design.
• Revised attention note in Understanding the Reset Release IP Requirement.
• Added important note about the RSU SDM Command Use Case in Operation Commands.
• Revised Command List and Description table. Updated description for:
  • CONFIG_STATUS
  • RSU_STATUS
• Added new topic: Generating the Initial RSU Image Using .rbf Files
• Corrected minor errors and spelling mistakes.

• Added a CvP-related note in the Intel® Agilex™ Configuration Overview.
• Revised block diagram descriptions in the Intel® Agilex™ Configuration Architecture.
• Revised Intel® Agilex™ Configuration Timing Diagram.
  • Added a note in the Reconfiguration Timing section.
  • Re-ordered sections for clarity.
• Revised Intel® Agilex™ Configuration Flow Diagram section.
  • Renamed Power Up section to Power-On to align the description with figure.
  • Merged Configuration Start and Configuration Pass sections into the FPGA Configuration section.
  • Renamed Configuration Error section to Failed FPGA Configuration.
  • Minor re-ordered sections for clarity.
  • Removed JTAG Configuration section. Reposition the existing JTAG configuration note.
  • Moved device response content to a new section: Device Response to Configuration and Reset Events.
• Removed DATA UNLOCK signal from the Available SDM I/O Pin Assignments for Configuration Signals that Do Not Use Dedicated SDM I/O Pins. DATA UNLOCK is not available for Intel® Agilex™ devices.
• Revised text and figure in SDM I/O Pins for Power Management and SmartVID
• Revised OSC_CLK_1 requirements in OSC_CLK_1 Clock Input
• Added new topic: Intel® Agilex™ Configuration Time Estimation
• Added new PFL II IP-related topics:
  • PFL II IP Recommended Constraints for Other Input Pins
  • PFL II IP Recommended Constraints for Other Output Pins
• Corrected T_{ext_delay} maximum value for OSC_CLK_1 configuration clock source at 166 MHz from 15 ns to 13.5 ns in the t_{ext_delay} as a Function of AS_CLK Frequency table.
• Revised AS_CLK topic:
  • Updated OS_CLK_1 description in the Supported Configuration Clock Source and AS_CLK Frequencies in Intel® Agilex™ Devices table. Added table's description.
  • Added note to clarify configuration behavior for invalid AS_CLK setting.
• Corrected address in the Debugging Guidelines for the AS Configuration Scheme. The firmware load should start from addresses 0, 512k, 1024k, and 1536k.
• Revised the steps for image update in the Updates with the Factory Update Image section.
• Revised Command List and Description table. Updated description for:
  • RSU_STATUS
  • QSPI_OPEN
  • QSPI_SET_CS
  • QSPI_ERASE
• Revised RSU Image Layout in Flash - SDM Perspective. Updated max_retry parameter value description.
• Revised step 2 in the Command Sequence To Perform Quad SPI Operations. The QSPI_SET_CS* command is optional for the AS x4 configuration and mandatory for the JTAG configuration scheme.
• Added new topic: Firmware Version Information
• Clarified usage of Use relative address option in the Application Image Layout and Generating an Application Image sections.
• Added new video guide about debugging SDM-related configuration issues in Intel® Agilex™ Debugging Guide.
• Updated the following figures and diagrams:
  • Intel® Agilex™ Configuration Interfaces
  • Power-On, Configuration, and Reconfiguration Timing Diagram
  • Recoverable Error during Reconfiguration Timing Diagram
  • Intel® Agilex™ FPGA Configuration Flow
  • SDM I/O pins selection in the Specifying Optional Configuration Pins section
  • Configuration Pin Selection in the Quartus® Prime Pro Edition Software
  • Dual-purpose pins selection in the Enabling Dual-Purpose Pins section
  • Specifying the Slave Device Type for Power Management and VID
  • Specifying the Page Command Setting
  • Configuration clock source selection in the Setting Configuration Clock Source section
  • AS configuration scheme setting in the Active Serial Configuration Software Settings section
• Corrected minor errors and spelling mistakes.

• Revised footnote in the Intel® Agilex™ Configuration Scheme, Data Width, and MSEL table. CvP protocol is not available for the PCIe* Gen3x8 and Gen4x8 in the P-tile device.
• Revised Additional Clock Requirements for HPS and Transceivers. Removed mention of PCIe and HBM2 IP.
• Updated MSEL Settings topic.
  • Updated footnote for AS Fast mode. To support this mode, all power supplies must ramp-up to the recommended operating condition within 10 ms.
  • Added footnote for AS Normal mode. To support the mode, the V_{CCIO_SDM} supply must ramp-up to the recommended operation condition within 10 ms.
  • Revised Updating Decision Firmware. Added statement about using a combined application image to update the decision firmware.
• Restructured PFL II IP content in the Avalon® -ST Configuration chapter.
• Added statement in The AVST_READY Signal. The PFL II IP core includes the AVST_READY synchronizer logic if you use PFL II IP core as the configuration host.
• Added note in the PFL II IP Functional Description. The PFL II IP does not support HPS cold reset.
• Added new topics:
  • Designing with the PFL II IP Core for Avalon-ST Single Device Configuration
  • Constraining the PFL II IP Core
  • PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins
  • PFL II IP Recommended Design Constraints for Using QSPI Flash
  • PFL II IP Recommended Design Constraints for Using CFI Flash
• Added new QSPI flash recommendation for PCIe designs in the AS Configuration Scheme Hardware Components and File Types section.
• Revised Debugging Guidelines for the AS Configuration Scheme to clarify AS Fast mode ramp-up power supplies requirement of 10 ms.
• Revised statement in the Including the Reset Release Intel FPGA IP in Your Design chapter regarding holding Reset Release Intel FPGA IP in reset after configuration is complete. Removed the INIT_DONE signal dependency.
  • Removed Assigning INIT_DONE To an SDM_IO Pin.
• Revised RSU_IMAGE_UPDATE description in the Command List and Description table.
• Restructured Operation Commands. Removed major and minor error code descriptions for the CONFIG_STATUS and RSU_STATUS commands. The major and minor error codes are now documented as an appendix in the Mailbox Client Intel® FPGA IP User Guide.
• Added new Use relative address parameter description in the Generating an Application Image section.
  • Updated the Specifying Parameters for an Application .rpd Stored in Flash Memory figure to include the new parameter.
• Revised the General Configuration Debugging Checklist table. The SDM debug toolkit is not available for the Intel® Agilex™ devices.
• Revised Understanding Configuration Status Using quartus_pgm command. Added quartus_pgm command for clarity.

• Revised CvP description in the Intel® Agilex™ Configuration Overview.
• Revised Specifying Boot Order for Intel® Agilex™ SoC Devices topic. Added text stating that FPGA reconfiguration is not allowed in the FPGA configuration first mode.
• Revised Intel® Agilex™ Configuration Architecture topic. Removed description of specific blocks for Intel® Agilex™ variants. Referred user to the Device Overview for latest information.
• Revised Additional Clock Requirements for HPS, PCIe* , and HBM2 topic.
  • In the FPGA configuration section, removed P-tile specific REFCLK_GXP clock.
  • Added text states that the clock frequencies must match the frequency setting specified in the Quartus® Prime software.
• Revised SDM Pin Mapping. Removed text stating that all SDM input signals include Schmitt triggers and all SDM outputs are open collector.
• Revised Enabling Dual-Purpose Pins. AVST_READY is not a dual-purpose pin.
• Updated configuration pin screenshot in the Specifying Optional Configuration Pins section.
• Revised SDM I/O Pins for Power Management and SmartVID topic. Updated screenshot and list of recommended devices.
• Added clarifying text in the OSC_CLK_1 Clock Input topic. If you use transceivers, you must provide an external clock to the OSC_CLK_1 clock input.
• Globally added AS_nRST configuration pin.
• Updated AS Configuration.
  • Added text describing QSPI flash reset.
  • Removed 108 MHz support from the Supported configuration clock source and AS_CLK Frequencies in Intel® Agilex™ Devices table.
  • Updated AS_CLK supported frequency from 133 MHz to 166 MHz.
  • Updated AS mode maximum data rate from 532 MHz to 664 MHz.
• Globally added support for new AS_CLK frequency. The frequency value is 166 MHz. Globally updated tables specifying AS configuration clock source range.
• Updated Programming Serial Flash Devices using the AS Interface and Debugging Guidelines for the AS Configuration Scheme with the following text: When you power up the Intel® Agilex™ with an empty serial flash device and use the AS interface to program the .rpd file into this serial flash device, you must power cycle the Intel® Agilex™ device to configure the device from the flash successfully.
• Added new debugging suggestions in the following topics:
  • Debugging Guidelines for the Avalon® -ST Configuration Scheme
  • Debugging Guidelines for the AS Configuration Scheme
  • Debugging Guidelines for the JTAG Configuration Scheme
• Added new debugging suggestion in the Debugging Guidelines for the JTAG Configuration Scheme stating that no external components should drive nSTATUS signal low during power up.
• Corrected CFI flash memory device number in Generating and Programing a .pof into SFI Flash. The device number is MT28EW.
• Moved nCONFIG, nSTATUS, CONF_DONE and INIT_DONE, and SDM_IO Pins sections from Understanding and Troubleshooting Configuration Pin Behavior to Specifying Optional Configuration Pins.
  • Removed debugging suggestions sections.
  • Revised resistor value from 25 kΩ to 20kΩ in the SDM_IO Pins section.
• Updated nSTATUS topic to clarify nSTATUS during the V_{CCIO_SDM} ramp up.
• Updated the Command List and Description table:
  • Corrected response length from 1 to 0 for the QSPI_OPEN, QSPI_CLOSE and QSPI_SET_CS command.
  • Revised RSU_IMAGE_UPDATE command description to include information about resetting QSPI flash and behavior between the external host and FPGA.
  • Revised QSPI_OPEN, QSPI_WRITE, QSPI_READ_DEVICE_REG, and QSPI_WRITE_DEVICE_REG commands descriptions to include information about resetting QSPI flash.
• Added new topic: Error Code Recovery.
• Added note in the Sub-Partition Table Layout (SPT Layout) stating that firmware doesn't read the SPT for non-HPS RSU operations.
• Revised step 2 in the Command Sequence To Perform Quad SPI Operations. You must issue the QSPI_SET_CS* command regardless of the configuration scheme.
• Revised CONF_DONE and INIT_DONE topic.
• Corrected minor errors and spelling mistakes.

• Updated QSPI_WRITE and QSPI_READ descriptions in the Command List and Description table. The text specifies that the maximum transfer size is 4 kilobytes or 1024 words.
• Updated note in the Adding an Application Image. The note states: When using HPS to manage RSU, you must update both copies of the Configuration Pointer Block (CBP0 and CBP1) and the sub-partition table (SPT). In a non-HPS case, while updates to the pointer blocks are mandatory, the updates to the sub-partition table are not required.

• Updated the Additional Clock Requirement for HPS, PCIe, eSRAM, and HBM2 section.
  • Added HPS_OSC_CLK clock in the FPGA Configuration topic.
  • Added new topic: HPS First Configuration.
• Globally corrected the AS_nCSO pin name.
• Globally removed dual-purpose text from the MSEL pin description. After power on reset, the MSEL pins can be repurposed as chip select pins. However, you cannot reuse the MSEL pins for other purpose.

• Added note on using the Parallel Flash Loader to program multiple QSPI flash devices in the IP for Use with the
                 Avalon®
              -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core: Functional Description section.

• Corrected I/O voltage standard in the Debugging Guidelines for the Avalon® -ST Configuration Scheme section. The I/O Bank 3A supports 1.2 V, not 1.8V.
• Removed outdated note specific to the MSEL pins from the Avalon® -ST Single-Device Configuration section.
• Added a new recommendation on clearing the RSU_STATUS command after the JTAG reconfiguration in the Debugging Guidelines for the JTAG Configuration Scheme section.
• Updated the Error Codes table. Added new error code responses:
  • HW_ERROR
  • COMMAND_SPECIFIC_ERROR
• Removed outdated text from the Understanding the Reset Release IP Requirement section. The text stated that an Quartus® Prime Pro Edition legality check prevents you from instantiating more than one instance of the Reset Release Intel FPGA IP.
• Removed anti-tamper protection feature from the Device Security section. Anti-tamper is not available in the Quartus® Prime Pro Edition software version 20.3.
• Revised text on error detection and correction in the Understanding SEUs section. The text states that the LSM firmware provides SEU single bit error and double adjacent bit error detection and correction. The multi-bit error and non-adjacent bit error are detected, but cannot be corrected.

• Updated Intel® Agilex™ Configuration Overview:
  • Renamed Intel® Agilex™ Configuration Data Width, Clock Rates, and Data Rates table to Intel® Agilex™ Configuration Scheme, Data Width,and MSEL.
  • Revised CvP section.
  • In the AS Fast Mode section, clarified difference between AS normal mode and AS fast mode.
• Revised configuration bitstream authentication statement in the Secure Device Manager section. During the configuration Start state, the SDM authenticates the the Intel-generated configuration firmware and configuration bitstream, ensuring that configuration bitstream is from a trusted source.
• Added Programmer link in the Updating the SDM Firmware section.
• Updated Intel® Agilex™ Configuration Timing Diagram section:
  • Updated the Intel® Agilex™ Configuration Timing Diagram figure:
    • Renamed figure from Configuration, Reconfiguration, and Error Timing Diagram to Power On, Configuration, and Reconfiguration Timing Diagram.
    • Aligned Power On Reset line depicted in the figure with the Power On configuration state.
    • Aligned nSTATUS, MSEL[2:0], and AVST_READY signals with the transition between Power On and SDM Start configuration state.
    • Reduced a gap between nCONFIG rising edge and nSTATUS rising edge to emphasize a very small time period.
    • Updated GPIO Status signal during Reconfiguration stage.
    • Removed Configuration Error portion of the timing diagram. Added separate timing diagram for the recoverable and unrecoverable configuration error in the Configuration Error section.
  • Renamed Configuration Error section to Recoverable Configuration Error. Added timing diagram. Revised nCONFIG content.
  • Added new section: Unrecoverable Configuration Error. Added timing diagram for unrecoverable error during the reconfiguration.
  • Revised statement on I/O pins in the POR state in the Power Supply Status section. I/O pins and programming registers remain as don't care if POR doesn't meet the specified time.
• Updated Intel® Agilex™ Configuration Flow Diagram:
  • Revised the Intel® Agilex™ FPGA Configuration Flow diagram.
  • Revised Power Up section.
  • Added text in the Configuration Start section specifying that the power management activity is ongoing during configuration.
  • In the JTAG Configuration section, added text: If an error occurs during JTAG configuration, the SDM does not assert nSTATUS signal. You can monitor the error messages that the Quartus® Prime Pro Edition Programmer generates for error reporting.
  • Added new section: Device Response to Configuration and Reset Events.
• Added clarification on E-tile variants in the Additional Clock Requirements for HPS, PCIe* , eSRAM, and HBM2 section. Replaced E-tile variants with E-tile transceiver reference clocks.
• Updated figure in the Specifying Optional Configuration Pins section.
• Updated OSC_CLK_1 Clock Input:
  • Added text: When you specify OSC_CLK_1 for configuration, the OSC_CLK_1 clock must be a stable and free-running clock..
  • Corrected OSC_CLK_1 frequency range in the OSC_CLK1 Input section. The frequency range is 160-230 MHz.
  • Removed .qsf file example. Use the Quartus® Prime Pro Edition GUI to specify frequencies.
  • Expanded topic to include additional usage requirements.
• Removed the following sections from the Avalon® -ST Configuration scheme:
  • QSF Assignment for Avalon® -ST x8
  • QSF Assignment for Avalon® -ST x16
  • QSF Assignment for Avalon® -ST x32
• Added the following restriction in the Avalon® ST Configuration section: Access to the I/O pins located in bank 3A with pin index[91...95] is not allowed for the AVSTx16 or x32 configuration scheme. You must leave these pins unconnected. For more information, refer to the device pin mapping files to identify the exact pin location.
• Updated AS Configuration section:
  • Revised Required Configuration Signals for the AS Configuration Scheme table. Removed outdated table description.
  • Revised AS_nCSO statement in the MSEL Pin Function for the AS x4 Configuration Scheme section.
  • Corrected OSC_CLK_1 frequency from 80 MHz to 71.5 MHz in the Maximum AS_CLK Frequency as a Function of Board Capacitance Loading and Clock Source and the Supported Configuration Clock Source and AS_CLK Frequencies in Intel® Agilex™ Devices table.
  • Added new table: T_{ext_delay} as a Function of AS_CLK Frequency in the AS Configuration Timing Parameters section.
  • Added notes in the Supported configuration clock source and AS_CLK Frequencies in Intel® Agilex™ Devices table clarifying that you observe a lower AS_CLK frequency when accessing the flash during user mode.
  • Revised step describing the programming file(s) generation in the Generating Programming Files using the Programming File Generator. Added command to save the programming file.
• Removed guidelines related to SD/MMC device configuration in the following sections:
  • Removed SD/MMC flash memories support in the Intel® Agilex™ Configuration Overview section.
  • Removed SD/MMC configuration scheme from the Intel® Agilex™ Configuration Data Width, Clock Rates, and Data Rates table.
  • Removed SD/MMC interface from the Intel® Agilex™ Configuration Interfaces figure.
  • Removed SD/MMC block from the SDM Block Diagram figure and the corresponding description.
  • Removed SD/MMC x4/x8 configuration scheme from the MSEL Settings for Each Configuration Scheme of Intel® Agilex™ Devices table.
  • Removed SD/MMC text from the CLIENT_ID_NO_MATCH description in the Error Codes table.
• Updated the JTAG Configuration section to include .rbf file as supported option to configure FPGA using the Quartus® Prime Programmer.
• Updated recommendations on how to debug the OSC_CLK_1 clock based configuration in the Debugging Guidelines for the AS Configuration Scheme topic.
• Removed UNKNOWN_BR error from the Error Codes table.
• Removed PUF data from flash memory section and figures. For more information, refer to the Intel Stratix 10 Device Security User Guide.
• Revised step on selecting factory and application images in the Generating the Initial RSU Image and the Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image sections.
• Revised flash offset for factory image, sub-partition tables, pointer blocks, and application images in the Flash Sub-Partitions Layout table.
• Added guidance on increasing the reserved memory space for factory and application images in the RSU Sub-Partitions Layout section. Revised flash offsets in the Flash Sub-Partitions Layout table.
• Revised System and Read only flag description in the Flags Specifying Contents and Access table.
• Added note and offset for the first image pointer slot in the Pointer Block Layout table. The offset is 0x20.
• Revised item 2 in the General Configuration Debugging Checklist table. Added PWRMGT_SDA and PWRMGT_SCL resistors.
• Added new topic: Understanding Configuration Status using quartus_pgm Command.
• Corrected minor errors and spelling mistakes.

• Updated maximum supported AS_CLK frequency in the Maximum AS_CLK Frequency as a Function of Board Capacitance Loading and Clock Source table. The AS_CLK maximum frequency for 37 pF capacitance loading using OS_CLK_1 as a clock source is 71.5 MHz, not 80 MHz.
• Removed 80 MHz support from the Supported configuration clock source and AS_CLK Frequencies in Intel® Agilex™ Devices table.

• Corrected Data Width (bits) field for CvP in Table 1. Intel® Agilex™ Configuration Data Width, Clock Rates, and Data Rates. Intel® Agilex™ support x8 and x16 CvP for the Gen3 and Gen4 data rates.

• Added a new chapter covering the Reset Release Intel® FPGA IP and why it must be included in your design.
• Added the following components to the Required Communication and Host Components for the Remote System Update Design Example figure:
  • Reset Release Intel® FPGA IP
  • Reset Bridge Intel® FPGA IP
  the to the RSU design example shown the
• Updated Remote System Update (RSU) chapter to provide accurate addresses for Intel® Agilex™ devices.
• Updated Remote System Update (RSU) chapter to provide figures with Intel® Agilex™ devices.
• Added the following text to the OSC_CLK_1 Clock Input topic: When you specify OSC_CLK_1 for configuration and reconfigure without powering down the Intel® Agilex™ device, the device can only reconfigure with OSC_CLK_1. In this scenario, OSC_CLK_1 must be a free-running clock.
• Added the following text to the definition of the Failing image field of the RSU_STATUS command:
  Note: A rising edge on nCONFIG to reconfigure from ASx4, does not clear this field. Information about failing image only updates when the Mailbox Client receives a new RSU_IMAGE_UPDATE command and successfully configures from the update image.
• Added the following restriction to the definition of QSPI_SET_CS: Access to the QSPI flash memory devices using SDM_IO pins is only available for the AS x4 configuration scheme, JTAG configuration, and a design compiled for ASx4 configuration. For the Avalon® ST configuration scheme, you must connect QSPI flash memories to GPIO pins.
• Removed support for a 16-byte Version ID as the first 16 bytes of the application image. This feature is not supported in Intel® Agilex™ devices.
• Updated the final suggestion in Debugging Guidelines for the JTAG Configuration Scheme topic, to the following: When the MSEL setting on the PCB is not JTAG, if you use the JTAG interface for reconfiguration after an initial reconfiguration using AS or the Avalon® -ST interface, the .sof must be in the file format you specified in the Quartus® Prime project. For example, if you initially configure the MSEL pins for AS configuration and configure using the AS scheme, a subsequent JTAG reconfiguration using a .sof generated for Avalon® -ST fails.

• Corrected definition of RSU_STATUS command. This command has 9, not 10 words.
• Added E-Tile Transceivers May Fail To Configure to the Debugging chapter.
• Revised the Modifying the List of Application Images topic.

Made the following changes to the device and software:

• Added the optional nCATTRIP (catastrophic trip) SDM I/O signal.
• Added the an eighth word to the to the RSU_STATUS response: Word 8: Current image retry counter.
• Added new field to the 5th word of the RSU_STATUS response. This field specifies the source of a reported error.
• Added RSU_NOTIFY to the available operation commands.
• Changed the number of images that the Programming File Generator supports from 3 to 7.
• Removed write restrictions for lower addresses in flash memory. (The device firmware must still reside at address 0x0.)

Made the following changes to the user guide:

• Added many topics showing how to implement in the Quartus® Prime Pro Edition Software.
• Changed the err status pulse range from 1 ms ±50% to 0.5 ms to 10 ms.

• Removed the SDM Firmware state from the Intel Intel® Agilex™ FPGA Configuration Flow diagram. This state is part of the FPGA Configuration state.

• Updated recommendations on how to debug a corrupt configuration bitstream for the AS x4 configuration scheme in the Debugging Guidelines for the AS Configuration Scheme topic.

• Corrected the signal name in The AVST_READY Signal topic: The device can starting sending data when AVST_READY asserts.
• Added note that the Avalon® ST x32 configuration scheme is limited to 3, DDR x72 DDR external memory interfaces. The Avalon® ST x8 and x16 configuration schemes can support up to 4, x72 DDR external memory interfaces.
• Corrected the Pin Type in the Required Configuration Signals for the Avalon® -ST Configuration Scheme table. AVSTx8_READY is an SDM I/O pin. AVST_READY is a GPIO or Dual-Purpose pin.
• Corrected minor errors and typos.

Made the following changes:

• Corrected Step 3 in the Initial Configuration Timing description. The step should say, with nConfig low, the SDM enters Idle mode after booting.
• Added note that designs using Avalon® -ST x16 and x32 configuration scheme may need to include a voltage translator between the FPGA and external host because some signals, to accommodate the GPIO pins that only support the 1.2 V I/O standard and the SDM I/O pins require a 1.8 V power supply.
• Created separate topic covering partial configuration.
• Revised and reorganized all topics covering configuration pin assignments:
  • Clarified the behavior of the MSEL pins in AS x4 mode.
  • Added information about the SDM_IO pin states during power-on and after device cleaning to the Intel® Agilex™ Configuration Pins topic.
  • Created separate topics covering partial configuration and SmartVID signals.
• Made the following changes to the RSU chapter:
  • Added the following topics:
    • RSU Glossary
    • Standard (non-RSU) Flash Layout
    • RSU Flash Layout – SDM Perspective
    • RSU Flash Layout – Your Perspective
    • Detailed Quad SPI Flash Layout
    • Sub-partitions Layout
    • Sub-Partition Table Layout
    • CMF Pointer Block Layout
    • Modifying the List of Application Images
    • Application Image Layout
    • Command Sequence To Perform Quad SPI Operations
  • The static firmware has been replaced by decision CMF.
  • The update image now includes the factory image, the decision CMF and the decision CMF data.
  • The QSPI_ERASE command is now 4 KB aligned. The number of words to erase must be a multiple of 1024.
  • Added definitions of major and minor error codes for RSU_STATUS and CONFIG_STATUS.
• Added footnote explaining that before you can use CvP you must configure either the periphery image or the full image via the AS configuration scheme. Then, you can configure the core image using CvP.
• Added recommendation to use the Analog Devices LTM4677 device to regulate the PMBus for SmartVID devices. You set this parameter here: Device > Device and Pin Options > Power Management & VID > Slave device type.
• Corrected maximum speed and data rate in the Intel® Agilex™ Configuration Data Width, Clock Rates, and Data Rates table. The Max Clock Rate is 33 MHz. The Max Data Rate is 33 Mbps.
• Added the eSRAM clocks to the list of free-running clocks that must be stable before configuration begins.
• The Reset Release Intel® Agilex™ FPGA IP is now available for Intel® Agilex™ devices.
• Removed vector for Power_Supply_Status in the Configuration, Reconfiguration, and Error Timing Diagram figure.
• Corrected the Intel® Agilex™ FPGA Configuration Flow diagram. The transition between FPGA Config* and User Mode should say INIT_DONE = HIGH.
• Corrected the following statement in the Debugging Guidelines for the JTAG Configuration Scheme topic: An nSTATUS falling edge terminates any JTAG access and the device reverts to the MSEL-specified boot source. nSTATUS must be stable during JTAG configuration.. In both sentence, nSTATUS should be nCONFIG.
• Removed pin assignments for CVP_CONFDONE for the Avalon® -ST in the Available SDM I/O Pin Assignments for Configuration Signals that Do Not Use Dedicated SDM I/O Pins table. CvP does not the support Avalon® -ST x8 configuration scheme in Intel® Agilex™ devices.