AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

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ID 683671
Date 6/12/2018
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Document Table of Contents
Document Table of Contents x
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices x
Features Hardware and Software Requirements Functional Description Simulation Hardware Testing Interface Signals Configuration Registers and Status Registers Document Revision History for AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Functional Description x
Design Components Clocking and Reset Scheme
Simulation x
Procedure Testbench Test Case
Hardware Testing x
Hardware Setup Test Procedure
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

Testbench

Figure 3. Testbench
Table 2.  Component Description
Component Description
Device under test (DUT) Components of the design that is tested in this simulation. This DUT consists of MAC and PHY.
Avalon® driver Consists of Avalon® -ST master bus functional models (BFMs). This driver forms the TX and RX paths. This driver also provides access to the Avalon® -MM interface of the DUT.
Ethernet Packet Monitor Monitors TX and RX datapaths, and displays the frames in the simulator console.
Table 3.  Testbench File DescriptionsThe testbench files below are needed to perform the simulation and these files are located in <project_directory>/simulation/ed_sim/models.
Component Description
avalon_bfm_wrapper.sv Wrapper for Avalon® BFM that is used by the Avalon_driver.sv.
avalon_driver.sv SystemVerilog HDL driver that uses the BFMs to form the transmit and receive path and access the Avalon® -MM interface.
avalon_if_param_pkg.sv SystemVerilog HDL testbench that contains parameters to configure the BFMs. The configuration is specific to DUT. As such, the content of this file should not be changed.
avalon_st_eth_packet_monitor.sv SystemVerilog HDL testbench that monitors the Avalon® -ST transmit and receive interfaces.
eth_register_map_params_pkg.sv SystemVerilog HDL package that maps addresses to Avalon® -MM control registers.
default_test_params_pkg.sv SystemVerilog HDL package that defines the test parameters for MAC configuration and Ethernet packet generation.
eth_mac_framce.sv SystemVerilog HDL testbench that handles the creation of Ethernet frame content.
tb_run.tcl TCL scripts that starts a simulation session of the DUT and other logic blocks.
tb_top.sv Top-level testbench file that consists of the DUT and other logic blocks.
wave.do Signal tracing macro script that the ModelSim* simulator uses to display testbench signals.
Level Two Title