AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

Download PDF
ID 683671
Date 6/12/2018
Public
Document Table of Contents
Document Table of Contents x
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices x
Features Hardware and Software Requirements Functional Description Simulation Hardware Testing Interface Signals Configuration Registers and Status Registers Document Revision History for AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Functional Description x
Design Components Clocking and Reset Scheme
Simulation x
Procedure Testbench Test Case
Hardware Testing x
Hardware Setup Test Procedure
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

Clocking and Reset Scheme

Figure 2. Clocking and Reset SchemeThis figure shows the clocking and reset scheme for this reference design. In this design’s top level, there are two external clock sources, ref_clk_clk (644.53125 MHz) and csr_clk (125 MHz). There is one active-low and asynchronous master reset signal, master_reset_n in the top-level of this reference design. The master reset signal is used to reset all modules in the reference design.
Level Two Title