AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

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ID 683671
Date 6/12/2018
Public
Document Table of Contents
Document Table of Contents x
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices x
Features Hardware and Software Requirements Functional Description Simulation Hardware Testing Interface Signals Configuration Registers and Status Registers Document Revision History for AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Functional Description x
Design Components Clocking and Reset Scheme
Simulation x
Procedure Testbench Test Case
Hardware Testing x
Hardware Setup Test Procedure
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

Procedure

  1. Download the reference design from Design Store and restore the design using Intel® Quartus® Prime software.
  2. Launch the Intel® Quartus® Prime software and open the project file (top.qpf).
  3. Before running the design compilation, click Assignments > Settings. Select Always regenerate design files for IP cores and Generate IP simulation model when generating IP under IP Settings category.
  4. To compile the design, click Processing > Start Compilation.
  5. Ensure that QUARTUS_ROOTDIR environment variable is pointing to the installation path of the Intel® Quartus® Prime software.
  6. Launch the ModelSim* -SE 10.6c and change the directory to <project_directory>/simulation/ed_sim/mentor.
  7. Run the following command to set up the required libraries, compile the functional simulation model, and exercise the simulation model with the provided testbench: 
    do tb_run.tcl
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