AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

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ID 683671
Date 6/12/2018
Public
Document Table of Contents
Document Table of Contents x
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices x
Features Hardware and Software Requirements Functional Description Simulation Hardware Testing Interface Signals Configuration Registers and Status Registers Document Revision History for AN 849: Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices
Functional Description x
Design Components Clocking and Reset Scheme
Simulation x
Procedure Testbench Test Case
Hardware Testing x
Hardware Setup Test Procedure
Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices

Features

  • Single-channel LL 10GbE Intel® FPGA IP core and Transceiver Native PHY, which is operating at 10 Gbps.
  • 171.0 ns round-trip latency in simulation.
  • Support for sequential random burst test in the hardware test and configurable number of packets, payload-data pattern, and packet length of each burst.
  • Support for Ethernet packet transmission and reception through external SFP+ loopback path.
  • Support for packet monitoring on both TX and RX data paths.
  • Support for packet statistics report on both MAC transmitter (TX) and MAC receiver (RX).
  • Support for System Console user interface. Users can make use of this TCL-based interface to dynamically configure and monitor any registers in this reference design.
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