AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor

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ID 683661
Date 2/21/2017
Public
Document Table of Contents
Document Table of Contents x
1. Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor
1. Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor x
1.1. Remote System Upgrade with MAX 10 FPGA Overview 1.2. Abbreviations 1.3. Prerequisite 1.4. Requirements 1.5. Reference Design Files 1.6. Reference Design Functional Description 1.7. Reference Design Walkthrough 1.8. Document Revision History
1.6. Reference Design Functional Description x
1.6.1. Reference Design IP Core Components 1.6.2. The Nios II EDS Software Application Design
1.6.1. Reference Design IP Core Components x
1.6.1.1. Nios II Gen2 Processor 1.6.1.2. Altera On-Chip Flash IP Core 1.6.1.3. Altera Dual Configuration IP Core 1.6.1.4. Altera UART IP Core 1.6.1.5. Generic Quad SPI Controller IP Core
1.6.2. The Nios II EDS Software Application Design x
1.6.2.1. Updating Application Images Remotely 1.6.2.2. Triggering Reconfiguration Remotely
1.7. Reference Design Walkthrough x
1.7.1. Generating Programming Files 1.7.2. Programming the QSPI 1.7.3. Programming the FPGA with Initial Image using JTAG 1.7.4. Updating Image and Triggering Reconfiguration using UART
1.7.1. Generating Programming Files x
1.7.1.1. Generating files for QSPI Programming 1.7.1.2. Generating files for Remote System Upgrade
1.7.1.2. Generating files for Remote System Upgrade x
1.7.1.2.1. .pof Generation through Convert Programming Files
1. Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor

1.6.2.1. Updating Application Images Remotely

After you have transmitted a programming bit stream file using the Remote Terminal, the Nios II software application is designed do the following:

  1. Set the Altera On-Chip Flash IP core Control Register to un-protect the CFM1 & 2 sector.
  2. Perform sector erase operation on CFM1 and CFM2. The software polls the status register of the Altera On-Chip Flash IP core to ensure successful erase has been completed.
  3. Receive 4 bytes of bit stream at a time from stdin. Standard input and output can be used to receive data directly from the host terminal and print output onto it. Types of standard input and output option can be set through the BSP Editor in Nios II Eclipse Build tool.
  4. Reverses the bit order for each byte.
    Note: Due to the configuration of Altera On-Chip Flash IP Core, every byte of data needs to be reversed before writing it into CFM.
  5. Start to write 4 bytes of data at a one time into CFM1 and CFM2. This process continues until the end of programming bit stream.
  6. Polls the status register of Altera On-Chip Flash IP to ensure successful write operation. Prompts a message to indicate the transmission is complete.
    Note: If the write operation fails, the terminal will halt the bit stream sending process and generate an error message.
  7. Sets the Control Register to re-protect CFM1 and CFM2 to prevent any unwanted write operation.
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