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1.6.1.4. Altera UART IP Core
The UART IP core allows the communication of serial character streams between an embedded system in MAX 10 FPGA and an external device. As an Avalon-MM master, the Nios II processor communicates with the UART IP core, which is an Avalon-MM slave. This communication is done by reading and writing control and data registers.
The core implements the RS-232 protocol timing and provides the following features:
- adjustable baud rate, parity, stop, and data bits
- optional RTS/CTS flow control signals
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