AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor

ID 683661
Date 2/21/2017
Public
Document Table of Contents

1.6.1.5. Generic Quad SPI Controller IP Core

The Generic Quad SPI Controller IP core functions as an interface between MAX 10 FPGA, the external flash and the on-board QSPI flash. The core provides access to the QSPI flash through read, write and erase operations.

When the Nios II application expands with more instructions, the file size of the hex file generated from Nios II application will be larger. Beyond a certain size limit, the UFM will not have a sufficient space to store the application hex file. To solve this, you can use the external QSPI flash available on the MAX 10 FPGA Development kit to store the application hex file.