Visible to Intel only — GUID: nik1410565033286
Ixiasoft
Visible to Intel only — GUID: nik1410565033286
Ixiasoft
17.3.1. Link Hangs in L0 State
There are many reasons that link may stop transmitting data. The following table lists some possible causes.
Possible Causes |
Symptoms and Root Causes |
Workarounds and Solutions |
---|---|---|
Avalon‑ST signaling violates Avalon-ST protocol |
Avalon‑ST protocol violations include the following errors:
These errors are applicable to both simulation and hardware. |
Add logic to detect situations where tx_st_ready remains deasserted for more than 100 cycles. Set post‑triggering conditions to check for the Avalon‑ST signaling of last two TLPs to verify correct tx_st_sop and tx_st_eop signaling. |
Incorrect payload size |
Determine if the length field of the last TLP transmitted by End Point is greater than the InitFC credit advertised by the link partner. For simulation, refer to the log file and simulation dump. For hardware, use a third‑party logic analyzer trace to capture PCIe transactions. |
If the payload is greater than the initFC credit advertised, you must either increase the InitFC of the posted request to be greater than the max payload size or reduce the payload size of the requested TLP to be less than the InitFC value. |
Flow control credit overflows |
Determine if the credit field associated with the current TLP type in the tx_cred bus is less than the requested credit value. When insufficient credits are available, the core waits for the link partner to release the correct credit type. Sufficient credits may be unavailable if the link partner increments credits more than expected, creating a situation where the Intel L-/H-Tile Avalon-ST for PCI Express IP Core credit calculation is out-of-sync with the link partner. |
Add logic to detect conditions where the tx_st_ready signal remains deasserted for more than 100 cycles. Set post‑triggering conditions to check the value of the tx_cred_* and tx_st_* interfaces. Add a FIFO status signal to determine if the TXFIFO is full. |
Malformed TLP is transmitted |
Refer to the error log file to find the last good packet transmitted on the link. Correlate this packet with TLP sent on Avalon‑ST interface. Determine if the last TLP sent has any of the following errors:
|
Revise the Application Layer logic to correct the error condition. |
Insufficient Posted credits released by Root Port |
If a Memory Write TLP is transmitted with a payload greater than the maximum payload size, the Root Port may release an incorrect posted data credit to the Endpoint in simulation. As a result, the Endpoint does not have enough credits to send additional Memory Write Requests. |
Make sure Application Layer sends Memory Write Requests with a payload less than or equal the value specified by the maximum payload size. |
Missing completion packets or dropped packets |
The RX Completion TLP might cause the RX FIFO to overflow. Make sure that the total outstanding read data of all pending Memory Read Requests is smaller than the allocated completion credits in RX buffer. |
You must ensure that the data for all outstanding read requests does not exceed the completion credits in the RX buffer. |