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1. Datasheet
2. Quick Start Guide
3. Arria® 10 or Cyclone® 10 GX Parameter Settings
4. Physical Layout
5. Interfaces and Signal Descriptions
6. Registers
7. Reset and Clocks
8. Interrupts
9. Error Handling
10. PCI Express Protocol Stack
11. Transaction Layer Protocol (TLP) Details
12. Throughput Optimization
13. Design Implementation
14. Additional Features
15. Hard IP Reconfiguration
16. Testbench and Design Example
17. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Arria® 10 or Cyclone® 10 GX Avalon-ST Interface for PCIe Solutions User Guide Archive
D. Document Revision History
3.1. Parameters
3.2. Arria® 10 or Cyclone® 10 GX Avalon-ST Settings
3.3. Base Address Register (BAR) and Expansion ROM Settings
3.4. Base and Limit Registers for Root Ports
3.5. Device Identification Registers
3.6. PCI Express and PCI Capabilities Parameters
3.7. Vendor Specific Extended Capability (VSEC)
3.8. Configuration, Debug, and Extension Options
3.9. PHY Characteristics
3.10. Example Designs
5.1. Clock Signals
5.2. Reset, Status, and Link Training Signals
5.3. ECRC Forwarding
5.4. Error Signals
5.5. Interrupts for Endpoints
5.6. Interrupts for Root Ports
5.7. Completion Side Band Signals
5.8. Parity Signals
5.9. LMI Signals
5.10. Transaction Layer Configuration Space Signals
5.11. Hard IP Reconfiguration Interface
5.12. Power Management Signals
5.13. Physical Layer Interface Signals
16.4.1. ebfm_barwr Procedure
16.4.2. ebfm_barwr_imm Procedure
16.4.3. ebfm_barrd_wait Procedure
16.4.4. ebfm_barrd_nowt Procedure
16.4.5. ebfm_cfgwr_imm_wait Procedure
16.4.6. ebfm_cfgwr_imm_nowt Procedure
16.4.7. ebfm_cfgrd_wait Procedure
16.4.8. ebfm_cfgrd_nowt Procedure
16.4.9. BFM Configuration Procedures
16.4.10. BFM Shared Memory Access Procedures
16.4.11. BFM Log and Message Procedures
16.4.12. Verilog HDL Formatting Functions
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4.2. Hard IP Block Placement In Arria® 10 Devices
Arria® 10 devices include 1–4 hard IP blocks for PCI Express. The bottom left hard IP block includes the CvP functionality for flip chip packages. For other package types, the CvP functionality is in the bottom right block.
Note: Arria® 10 devices do not support configurations that configure a bottom (left or right) hard IP block with a Gen3 x4 or Gen3 x8 IP core and also configure the top hard IP block on the same side with a Gen3 x1 or Gen3 x2 IP core variation.
Figure 18. Arria® 10 Devices with 72 Transceiver Channels and Four PCIe Hard IP Blocks
Figure 19. Arria® 10 Devices with 96 Transceiver Channels and Four PCIe Hard IP Blocks
Figure 20. Arria® 10 GT Devices with 48 Transceiver Channels and Two PCIe Hard IP Blocks
Refer to the Arria® 10 Transceiver Layout in the Arria® 10 for comprehensive figures for Arria® 10 GT, GX, and SX devices.
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