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1. Datasheet
2. Quick Start Guide
3. Arria® 10 or Cyclone® 10 GX Parameter Settings
4. Physical Layout
5. Interfaces and Signal Descriptions
6. Registers
7. Reset and Clocks
8. Interrupts
9. Error Handling
10. PCI Express Protocol Stack
11. Transaction Layer Protocol (TLP) Details
12. Throughput Optimization
13. Design Implementation
14. Additional Features
15. Hard IP Reconfiguration
16. Testbench and Design Example
17. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Arria® 10 or Cyclone® 10 GX Avalon-ST Interface for PCIe Solutions User Guide Archive
D. Document Revision History
3.1. Parameters
3.2. Arria® 10 or Cyclone® 10 GX Avalon-ST Settings
3.3. Base Address Register (BAR) and Expansion ROM Settings
3.4. Base and Limit Registers for Root Ports
3.5. Device Identification Registers
3.6. PCI Express and PCI Capabilities Parameters
3.7. Vendor Specific Extended Capability (VSEC)
3.8. Configuration, Debug, and Extension Options
3.9. PHY Characteristics
3.10. Example Designs
5.1. Clock Signals
5.2. Reset, Status, and Link Training Signals
5.3. ECRC Forwarding
5.4. Error Signals
5.5. Interrupts for Endpoints
5.6. Interrupts for Root Ports
5.7. Completion Side Band Signals
5.8. Parity Signals
5.9. LMI Signals
5.10. Transaction Layer Configuration Space Signals
5.11. Hard IP Reconfiguration Interface
5.12. Power Management Signals
5.13. Physical Layer Interface Signals
16.4.1. ebfm_barwr Procedure
16.4.2. ebfm_barwr_imm Procedure
16.4.3. ebfm_barrd_wait Procedure
16.4.4. ebfm_barrd_nowt Procedure
16.4.5. ebfm_cfgwr_imm_wait Procedure
16.4.6. ebfm_cfgwr_imm_nowt Procedure
16.4.7. ebfm_cfgrd_wait Procedure
16.4.8. ebfm_cfgrd_nowt Procedure
16.4.9. BFM Configuration Procedures
16.4.10. BFM Shared Memory Access Procedures
16.4.11. BFM Log and Message Procedures
16.4.12. Verilog HDL Formatting Functions
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2.3. Generating the Design
Figure 7. Procedure
Follow these steps to generate the design from the IP Parameter Editor:
- In the IP Catalog (Tools > IP Catalog) locate and select the Arria® 10/Cyclone 10 Hard IP for PCI Express.
- Starting with the Quartus® Prime Pro 16.1 software, the New IP Variation dialog box appears.
- Specify a top-level name and the folder for your custom IP variation, and the target device. Click OK
- On the IP Settings tabs, specify the parameters for your IP variation.
- On the Example Designs tab, the PIO design is available for your IP variation.
Figure 8. Example Design Tab
- For Example Design Files, select the Simulation and Synthesis options.
- For Generated HDL Format, only Verilog is available.
- For Target Development Kit select the Arria® 10 FPGA Development Kit option.
Note: Currently, you cannot select an Cyclone® 10 GX Development Kit when generating an example design.
- Click the Generate Example Design button. The software generates all files necessary to run simulations and hardware tests on the Arria® 10 FPGA Development Kit. Click Close when generation completes.
- Click Finish.
- The prompt, Recent changes have not been generated. Generate now?, allows you to create files for simulation and synthesis. Click No to continue to simulate the design example you just generated.