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1. Datasheet
2. Quick Start Guide
3. Arria® 10 or Cyclone® 10 GX Parameter Settings
4. Physical Layout
5. Interfaces and Signal Descriptions
6. Registers
7. Reset and Clocks
8. Interrupts
9. Error Handling
10. PCI Express Protocol Stack
11. Transaction Layer Protocol (TLP) Details
12. Throughput Optimization
13. Design Implementation
14. Additional Features
15. Hard IP Reconfiguration
16. Testbench and Design Example
17. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Arria® 10 or Cyclone® 10 GX Avalon-ST Interface for PCIe Solutions User Guide Archive
D. Document Revision History
3.1. Parameters
3.2. Arria® 10 or Cyclone® 10 GX Avalon-ST Settings
3.3. Base Address Register (BAR) and Expansion ROM Settings
3.4. Base and Limit Registers for Root Ports
3.5. Device Identification Registers
3.6. PCI Express and PCI Capabilities Parameters
3.7. Vendor Specific Extended Capability (VSEC)
3.8. Configuration, Debug, and Extension Options
3.9. PHY Characteristics
3.10. Example Designs
5.1. Clock Signals
5.2. Reset, Status, and Link Training Signals
5.3. ECRC Forwarding
5.4. Error Signals
5.5. Interrupts for Endpoints
5.6. Interrupts for Root Ports
5.7. Completion Side Band Signals
5.8. Parity Signals
5.9. LMI Signals
5.10. Transaction Layer Configuration Space Signals
5.11. Hard IP Reconfiguration Interface
5.12. Power Management Signals
5.13. Physical Layer Interface Signals
16.4.1. ebfm_barwr Procedure
16.4.2. ebfm_barwr_imm Procedure
16.4.3. ebfm_barrd_wait Procedure
16.4.4. ebfm_barrd_nowt Procedure
16.4.5. ebfm_cfgwr_imm_wait Procedure
16.4.6. ebfm_cfgwr_imm_nowt Procedure
16.4.7. ebfm_cfgrd_wait Procedure
16.4.8. ebfm_cfgrd_nowt Procedure
16.4.9. BFM Configuration Procedures
16.4.10. BFM Shared Memory Access Procedures
16.4.11. BFM Log and Message Procedures
16.4.12. Verilog HDL Formatting Functions
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1.3. Device Family Support
The following terms define device support levels for Intel® FPGA IP cores:
- Advance support—the IP core is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
- Preliminary support—the IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
- Final support—the IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.
Device Family |
Support Level |
---|---|
Arria® 10 or Cyclone® 10 GX |
Final. |
Other device families |
Refer to the Intel's PCI Express IP Solutions web page for support information on other device families. |