AN 464: DFT/IDFT Reference Design

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ID 683644
Date 5/30/2018
Public
Document Table of Contents
Document Table of Contents x
About the DFT/IDFT Reference Design Functional Description for the DFT/IDFT Reference Design Getting Started with the DFT/IDFT Reference Design Running the Fixed-Point Model for the DFT/IDFT Reference Design Performance of DFT/IDFT Reference Design Document Revision History for AN 464: DFT/IDFT Reference Design
Functional Description for the DFT/IDFT Reference Design x
Parameters for the DFT/IDFT Reference Design Signals for the DFT/IDFT Reference Design
Getting Started with the DFT/IDFT Reference Design x
System Requirements for the DFT/IDFT Reference Design Installing the DFT/IDFT Reference Design Simulating the DFT/IDFT Reference Design with the Avalon-ST Testbench Simulating the Reference design with the Command Line Regression Test Synthezising the DFT/IDFT Reference Design
Running the Fixed-Point Model for the DFT/IDFT Reference Design x
Fixed-Point Model Parameters
About the DFT/IDFT Reference Design
Functional Description for the DFT/IDFT Reference Design
Getting Started with the DFT/IDFT Reference Design
Running the Fixed-Point Model for the DFT/IDFT Reference Design
Performance of DFT/IDFT Reference Design
Document Revision History for AN 464: DFT/IDFT Reference Design

Signals for the DFT/IDFT Reference Design

Table 3.  Signals
Name Direction Description
a_reset_n Input

Active low asynchronous reset. Deassert synchronously to clkto avoid reset-release timing violations.

clk Input System clock. All logic in the design is synchronous to this clock.
exponent[7:0] Output Avalon-ST source data. Exponent of all samples in the packet.A single value is valid throughout the packet on this output.
sink_eop Input Avalon-ST sink end of packet. The design does not use this signal.
sink_imag[datawidth-1:0] Input Avalon-ST sink data. Imaginary (Q) input sample.
sink_imag[iqinpercc * datawidth-1:0] Input -
sink_length[10:0] Input Transform length. A straight binary encoding of one of the lengths.The value on this input is sampled when sink_valid is high and sink_ready was high on the previous cycle.
sink_ready Output Avalon-ST Ready. The input interface has a ready latency of 1.
sink_real[datawidth-1:0] Input Avalon-ST sink data. Real (I) input sample.
sink_real[iqinpercc * datawidth-1:0]    
sink_sop Input Avalon-ST sink start of packet.
sink_valid Input Avalon-ST sink valid.
source_eop Output Avalon-ST source end of packet.
source_imag[datawidth- 1:0] Output Avalon-ST source data. Mantissa of Imaginary (Q) output sample.
source_imag_eng1[datawidth-1:0] Output Avalon-ST source data for dft engine 1.Mantissa of Imaginary (Q) output sample.
source_imag_eng2[datawidth-1:0] Output Avalon-ST source data for dft engine 2.Mantissa of Imaginary (Q) output sample.
source_imag_eng3[datawidth-1:0] Output Avalon-ST source data for dft engine 3.Mantissa of Imaginary (Q) output sample.
source_real_eng1[datawidth-1:0] Output Avalon-ST source data for dft engine 1.Mantissa of Real (I) output sample.
source_real_eng2[datawidth-1:0] Output Avalon-ST source data for dft engine 2.Mantissa of Real (I) output sample.
source_real_eng3[datawidth-1:0] . Output Avalon-ST source data for dft engine 3.Mantissa of Real (I) output sample,
source_ready_in Input Avalon-STsource ready. This signal is only enabled if the parameter use_output_buffer is set to 1. The ready latency is0.
source_sop Output Avalon-ST source start of packet.
source_valid Output Avalon-ST source valid.
Level Two Title