The DFT 3P3R block decomposes the input block into three sub-blocks and performs three parallel DFT operations. The DFT results feed a parallel radix-3 pipelined engine for the final radix-3 pass that computes the final DFT result. The DFT radix-3 engine output 3 IQ samples per clock cycle.

IQ output 1: [DATA 0]    [DATA 1]    [DATA 2]    ... [DATA 1079]
IQ output 2: [DATA 1080] [DATA 1081] [DATA 1082] ... [DATA 2159]
IQ output 3: [DATA 2160] [DATA 2161] [DATA 2162] ... [DATA 3239]

You can configure the number of input IQ samples per clock cycle for the Avalon-ST sink interface with parameter iqinpercc that has values of 1 and 3. Setting the IQ samples per clock cycle to 3 reduces the block load latency on the DFT reference design, provided that the targeted system can sustain the DFT input throughput.

You can configure the output Avalon-ST interface to come from the DFT engine from an optional buffer. The buffer depth is user selectable. With the buffer there is a ready signal input, which prevents data streaming out as soon as the DFT engine finishes a transform. When the DFT engine finishes a transform is determined by: when data is input to the design, and the transform time for the current length.

The reference design uses an Avalon-ST interface to output the transformed block into three parallel IQ sub-blocks.

If you turn on the output buffer, the ready input controls the data flow out of the buffer. The buffer always fills in bursts as the DFT engine completes individual transforms so you must ensure the buffer depth is adequate for your system to avoid overflow. The design behaves unpredictably if the buffer overflows.

The design provides the sop and eop signals at the output, which you can optionally use.

To perform an IDFT, set the idft_mode parameter to 1.

The design does not perform the 1/length scaling for an IDFT.